Chebyshev IIR filter sharpening implemented on FPGA - Telfor 2008
Chebyshev IIR filter sharpening implemented on FPGA - Telfor 2008 Chebyshev IIR filter sharpening implemented on FPGA - Telfor 2008
Select m sel Select In Gateway In System Generator reinterpret Resource Estimator Select n ↑9 Upsample m ↑2 Upsample n d0 d1 Mux 1 sel d0 d1 Mux 2 Hs(z) z -1 z -1 Hc(z) z -1 z -1 ↓9 Downsample m ↓2 Downsample n sel d0 d1 Mux 3 reinterpret Out Gateway Out Fig. 4. Implementation of a sharpened
- Page 1 and 2: Chebyshev
- Page 3: standard and compensation f
Select m<br />
sel<br />
Select<br />
In<br />
Gateway In<br />
System<br />
Generator<br />
reinterpret<br />
Resource<br />
Estimator<br />
Select n<br />
↑9<br />
Upsample m<br />
↑2<br />
Upsample n<br />
d0<br />
d1<br />
Mux 1<br />
sel<br />
d0<br />
d1<br />
Mux 2<br />
Hs(z)<br />
z -1<br />
z -1<br />
Hc(z)<br />
z -1<br />
z -1<br />
↓9<br />
Downsample m<br />
↓2<br />
Downsample n<br />
sel<br />
d0<br />
d1<br />
Mux 3<br />
reinterpret<br />
Out<br />
Gateway Out<br />
Fig. 4. Implementati<strong>on</strong> of a sharpened <str<strong>on</strong>g>IIR</str<strong>on</strong>g> <str<strong>on</strong>g>filter</str<strong>on</strong>g> that c<strong>on</strong>sists of two <str<strong>on</strong>g>filter</str<strong>on</strong>g>s Hs(z) and Hc(z), c<strong>on</strong>trol circuits, two-input<br />
multiplexers and up-sample and down-sample blocks that c<strong>on</strong>trol the data rate through the <str<strong>on</strong>g>filter</str<strong>on</strong>g>s.<br />
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