40G MACsec Encryption in an FPGA - Ethernet Technology Summit
40G MACsec Encryption in an FPGA - Ethernet Technology Summit
40G MACsec Encryption in an FPGA - Ethernet Technology Summit
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<strong>MACsec</strong> IP Core Top Level<br />
Secure Ch<strong>an</strong>nel Parameters<br />
Controlled Output to System<br />
Uncontrolled Output to System<br />
Receive Path<br />
Input From MAC<br />
Controlled Input from System<br />
Uncontrolled Input from System<br />
Tr<strong>an</strong>smit Path<br />
Output to MAC<br />
Enable<br />
Clock<br />
Reset<br />
Control <strong>an</strong>d Statistics<br />
S<strong>an</strong> Jose, CA USA<br />
February 2012 6
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