40G MACsec Encryption in an FPGA - Ethernet Technology Summit

Algotronix MACsec Cores
• Design scalable from 1G to 10G and 40G
• Configurable number of Secure Channels
• Support worst case timing without overrun
• Portable to all major FPGA families
• Tier one customers can access our IP
through Xilinx
• VHDL or Verilog source code
• Comprehensive test bench
• Cost effective
San Jose, CA USA
February 2012 12