40G MACsec Encryption in an FPGA - Ethernet Technology Summit
40G MACsec Encryption in an FPGA - Ethernet Technology Summit
40G MACsec Encryption in an FPGA - Ethernet Technology Summit
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<strong>MACsec</strong> Core Area Guidel<strong>in</strong>es<br />
1G 10G <strong>40G</strong><br />
Regs 14602 17371 37486<br />
Slice<br />
LUTs<br />
RAM<br />
18ks<br />
RAM<br />
36ks<br />
17031 32119 42350<br />
4 4 55<br />
5 5 9<br />
Xil<strong>in</strong>x Virtex 5<br />
128 bit keys<br />
All MACSEC features <strong>in</strong>cluded<br />
Tr<strong>an</strong>smit <strong>an</strong>d Receive ch<strong>an</strong>nel <strong>in</strong>cluded<br />
AES Sboxes implemented <strong>in</strong> LUTs for 1G <strong>an</strong>d 10G designs<br />
Clock frequency is 2x higher for <strong>40G</strong> design<br />
Guidel<strong>in</strong>e only – m<strong>an</strong>y implementation options are possible<br />
S<strong>an</strong> Jose, CA USA<br />
February 2012 11
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