40G MACsec Encryption in an FPGA - Ethernet Technology Summit

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Challenges of AES-GCM at 40Gbit/sec • Start with existing AES-GCM 10Gbit design • Double clock frequency to 312.5MHz • Double number of pipeline stages in AES-CTR • Simplify and speed up keyschedule implementation • Algebraic manipulation of GF-multiply (feedback loop in GF-Hash makes pipelining difficult) • New Karatsuba GF multiplier design to improve speed and area San Jose, CA USA February 2012 10
MACsec Core Area Guidelines 1G 10G 40G Regs 14602 17371 37486 Slice LUTs RAM 18ks RAM 36ks 17031 32119 42350 4 4 55 5 5 9 Xilinx Virtex 5 128 bit keys All MACSEC features included Transmit and Receive channel included AES Sboxes implemented in LUTs for 1G and 10G designs Clock frequency is 2x higher for 40G design Guideline only – many implementation options are possible San Jose, CA USA February 2012 11
Page 1 and 2: 40G MACsec Encryption in an FPGA Dr
Page 3 and 4: MACsec Applications • MACsec can
Page 5 and 6: MACsec Function Destination Address
Page 7 and 8: Secure Channel Unit • The Algotro
Page 9: AES-GCM IP Core load_key input_key

40G MACsec Encryption in an FPGA - Ethernet Technology Summit

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