Current Mode PWM Controller (Rev. A)

Current Mode PWM Controller
FEATURES
• Optimized For Off-line And DC
To DC Converters
• Low Start Up Current (

ABSOLUTE MAXIMUM RATINGS(Note 1)
Supply Voltage (Low Impedance Source) ..............30V
Supply Voltage (ICC < 30mA) .................Self Limiting
Output Current. ..................................±1A
Output Energy (Capacitive Load) ....................5µJ
Analog Inputs (Pins 2, 3). ..................-0.3V to +6.3V
Error Amp Output Sink Current ....................10mA
Power Dissipation at TA ≤ 25°C (DIL−8).................1W
Power Dissipation at TA ≤ 25°C (SOIC-14) .........725mW
Storage Temperature Range. .............-65°C to +150°C
Junction Temperature Range .............-55°C to +150°C
Lead Temperature (soldering, 10 seconds) ...........300°C
Note 1: All voltages are with respect to Pin 5.
All currents are positive into the specified terminal.
Consult Packaging Section of Databook for thermal
limitations and considerations of packages.
UC1842/3/4/5
UC2842/3/4/5
UC3842/3/4/5
CONNECTION DIAGRAMS
DIL-8, SOIC-8 (TOP VIEW)
N or J Package, D8 Package
PLCC-20 (TOP VIEW)
Q Package
SOIC-14, CFP-14. (TOP VIEW)
D or W Package
PACKAGE PIN FUNCTION
FUNCTION
PIN
N/C 1
COMP 2
N/C 3
N/C 4
VFB 5
N/C 6
ISENSE 7
N/C 8
N/C 9
RT/CT 10
N/C 11
PWR GND 12
GROUND 13
N/C 14
OUTPUT 15
N/C 16
VC 17
VCC 18
N/C 19
VREF 20
DISSIPATION RATING TABLE
Package TA ≤ 25°C Derating Factor TA ≤ 70°C
TA ≤ 85°C TA ≤ 125°C
Power Rating Above TA ≤ 25°C Power Rating Power Rating Power Rating
W 700 mW 5.5 mW/°C 452 mW 370 mW 150 mW
2

ELECTRICAL CHARACTERISTICS:
UC1842/3/4/5
UC2842/3/4/5
UC3842/3/4/5
Unless otherwise stated, these specifications apply for -55°C ≤ TA ≤ 125°C for the
UC184X; -40°C ≤ TA ≤ 85°C for the UC284X; 0°C ≤ TA ≤ 70°C for the 384X; VCC = 15V
(Note 5); RT = 10k; CT = 3.3nF, TA=TJ.
UC1842/3/4/5 UC3842/3/4/5 UNITS
PARAMETER
TEST CONDITIONS
UC2842/3/4/5
MIN TYP MAX MIN TYP MAX
Reference Section
Output Voltage TJ = 25°C, IO = 1mA 4.95 5.00 5.05 4.90 5.00 5.10 V
Line Regulation 12 ≤ VIN ≤ 25V 6 20 6 20 mV
Load Regulation 1 ≤ I0 ≤ 20mA 6 25 6 25 mV
Temp. Stability (Note 2) (Note 7) 0.2 0.4 0.2 0.4 mV/°C
Total Output Variation Line, Load, Temp. (Note 2) 4.9 5.1 4.82 5.18 V
Output Noise Voltage 10Hz ≤ f ≤ 10kHz, TJ = 25°C (Note2) 50 50 µV
Long Term Stability TA = 125°C, 1000Hrs. (Note 2) 5 25 5 25 mV
Output Short Circuit -30 -100 -180 -30 -100 -180 mA
Oscillator Section
Initial Accuracy TJ = 25°C (Note 6) 47 52 57 47 52 57 kHz
Voltage Stability 12 ≤ VCC ≤ 25V 0.2 1 0.2 1 %
Temp. Stability TMIN ≤ TA ≤ TMAX (Note 2) 5 5 %
Amplitude VPIN 4 peak to peak (Note 2) 1.7 1.7 V
Error Amp Section
Input Voltage VPIN 1 = 2.5V 2.45 2.50 2.55 2.42 2.50 2.58 V
Input Bias Current -0.3 -1 -0.3 -2 µA
AVOL 2 ≤ VO ≤ 4V 65 90 65 90 dB
Unity Gain Bandwidth (Note 2) TJ = 25°C 0.7 1 0.7 1 MHz
PSRR 12 ≤ VCC ≤ 25V 60 70 60 70 dB
Output Sink Current VPIN 2 = 2.7V, VPIN 1 = 1.1V 2 6 2 6 mA
Output Source Current VPIN 2 = 2.3V, VPIN 1 = 5V -0.5 -0.8 -0.5 -0.8 mA
VOUT High VPIN 2 = 2.3V, RL = 15k to ground 5 6 5 6 V
VOUT Low VPIN 2 = 2.7V, RL = 15k to Pin 8 0.7 1.1 0.7 1.1 V
Current Sense Section
Gain (Notes 3 and 4) 2.85 3 3.15 2.85 3 3.15 V/V
Maximum Input Signal VPIN 1 = 5V (Note 3) 0.9 1 1.1 0.9 1 1.1 V
PSRR 12 ≤ V CC ≤ 25V (Note 3) (Note 2) 70 70 dB
Input Bias Current -2 -10 -2 -10 µA
Delay to Output VPIN 3 = 0 to 2V (Note 2) 150 300 150 300 ns
Note 2: These parameters, although guaranteed, are not 100% tested in production.
Note 3: Parameter measured at trip point of latch with VPIN 2 =0.
Note 4: Gain defined as
∆ VPIN 1
A = ≤VPIN
≤ V
∆ VPIN 3 , 0 3 08 .
Note 5: Adjust VCC above the start threshold before setting at 15V.
Note 6: Output frequency equals oscillator frequency for the UC1842 and UC1843.
Output frequency is one half oscillator frequency for the UC1844 and UC1845.
Note 7: Temperature stability, sometimes referred to as average temperature coefficient, is described by the equation:
VREF
( max) − VREF ( min)
Temp Stability =
TJ ( max) − TJ ( min)
VREF (max) and VREF (min) are the maximum and minimum reference voltages measured over the appropriate
temperature range. Note that the extremes in voltage do not necessarily occur at the extremes in temperature.
3

UC1842/3/4/5
UC2842/3/4/5
UC3842/3/4/5
ELECTRICAL CHARACTERISTICS: Unless otherwise stated, these specifications apply for −55°C ≤ TA ≤ 125°C for the
UC184X; −40°C ≤ TA ≤ 85°C for the UC284X; 0°C ≤ TA ≤ 70°C for the 384X; VCC =
15V (Note 5); RT = 10k; CT = 3.3nF, TA=TJ.
UC1842/3/4/5 UC3842/3/4/5 UNITS
PARAMETER
TEST CONDITION
UC2842/3/4/5
MIN TYP MAX MIN TYP MAX
Output Section
Output Low Level ISINK = 20mA 0.1 0.4 0.1 0.4 V
ISINK = 200mA 1.5 2.2 1.5 2.2 V
Output High Level ISOURCE = 20mA 13 13.5 13 13.5 V
ISOURCE = 200mA 12 13.5 12 13.5 V
Rise Time TJ = 25°C, CL = 1nF (Note 2) 50 150 50 150 ns
Fall Time TJ = 25°C, CL = 1nF (Note 2) 50 150 50 150 ns
Under-voltage Lockout Section
Start Threshold X842/4 15 16 17 14.5 16 17.5 V
X843/5 7.8 8.4 9.0 7.8 8.4 9.0 V
Min. Operating Voltage X842/4 9 10 11 8.5 10 11.5 V
After Turn On
X843/5 7.0 7.6 8.2 7.0 7.6 8.2 V
PWM Section
Maximum Duty Cycle X842/3 95 97 100 95 97 100 %
X844/5 46 48 50 47 48 50 %
Minimum Duty Cycle 0 0 %
Total Standby Current
Start-Up Current 0.5 1 0.5 1 mA
Operating Supply Current VPIN 2 =VPIN 3 = 0V 11 17 11 17 mA
VCC Zener Voltage ICC = 25mA 30 34 30 34 V
Note 2: These parameters, although guaranteed, are not 100% tested in production.
Note 3: Parameter measured at trip point of latch with VPIN 2 =0
.
Note 4:
∆ VPIN 1
Gain defined as: A = ≤VPIN
≤ V
∆ VPIN 3 0 3 08 Note 5: Adjust VCC above the start threshold before setting at 15V.
Note 6: Output frequency equals oscillator frequency for the UC1842 and UC1843.
Output frequency is one half oscillator frequency for the UC1844 and UC1845.
ERROR AMP CONFIGURATION
Error Amp can Source or Sink up to 0.5mA
4

UC1842/3/4/5
UC2842/3/4/5
UC3842/3/4/5
UNDER-VOLTAGE LOCKOUT
During under-voltage lock-out, the output driver is
biased to sink minor amounts of current. Pin 6 should
be shunted to ground with a bleeder resistor to prevent
activating the power switch with extraneous leakage
currents.
CURRENT SENSE CIRCUIT
OSCILLATOR SECTION
Peak Current (IS) is Determined By The Formula
ISMAX ′ 1.0V
RS
A small RC filter may be required to suppress switch transients.
5

UC1842/3/4/5
UC2842/3/4/5
OUTPUT SATURATION CHARACTERISTICS
ERROR AMPLIFIER OPEN-LOOP
FREQUENCY RESPONSE
OPEN-LOOP LABORATORY FIXTURE
High peak currents associated with capacitive loads necessitate
careful grounding techniques. Timing and bypass
capacitors should be connected close to pin 5 in a
single point ground. The transistor and 5k potentiometer
are used to sample the oscillator waveform and apply
an adjustable ramp to pin 3.
SHUT DOWN TECHNIQUES
Shutdown of the UC1842 can be accomplished by two
methods; either raise pin 3 above 1V or pull pin 1 below
a voltage two diode drops above ground. Either method
causes the output of the PWM comparator to be high
(refer to block diagram). The PWM latch is reset dominant
so that the output will remain low until the next
clock cycle after the shutdown condition at pin 1 and/or
3 is removed. In one example, an externally latched
shutdown may be accomplished by adding an SCR
which will be reset by cycling VCC below the lower
UVLO threshold. At this point the reference turns off, allowing
the SCR to reset.
6

UC1842/3/4/5
UC2842/3/4/5
UC3842/3/4/5
OFFLINE FLYBACK REGULATOR
Power Supply Specifications
1. Input Voltages 5VAC to 130VA
(50 Hz/60Hz)
2. Line Isolation 3750V
3. Switching Frequency 40kHz
4. Efficiency at Full Load 70%
5. Output Voltage:
A. +5V, ±5%; 1A to 4A load
Ripple voltage: 50mV P-P Max
B. +12V, ±3%; 0.1A to 0.3A load
Ripple voltage: 100mV P-P Max
C. -12V ,±3%; 0.1A to 0.3A load
Ripple voltage: 100mV P-P Max
SLOPE COMPENSATION
A fraction of the oscillator ramp can be resistively
summed with the current sense signal to provide
slope compensation for converters requiring duty
cycles over 50%.
7

PACKAGE OPTION ADDENDUM
www.ti.com
30-Mar-2005
PACKAGING INFORMATION
Orderable Device Status (1) Package
Type
Package
Drawing
Pins Package
Qty
Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
5962-8670401PA ACTIVE CDIP JG 8 1 TBD A42 SNPB Level-NC-NC-NC
5962-8670401VPA ACTIVE CDIP JG 8 1 TBD Call TI Level-NC-NC-NC
5962-8670401VXA ACTIVE LCCC FK 20 1 TBD Call TI Level-NC-NC-NC
5962-8670401XA ACTIVE LCCC FK 20 1 TBD POST-PLATE Level-NC-NC-NC
5962-8670402PA ACTIVE CDIP JG 8 1 TBD A42 SNPB Level-NC-NC-NC
5962-8670402VPA ACTIVE CDIP JG 8 1 TBD Call TI Level-NC-NC-NC
5962-8670402VXA ACTIVE LCCC FK 20 1 TBD Call TI Level-NC-NC-NC
5962-8670402XA ACTIVE LCCC FK 20 1 TBD POST-PLATE Level-NC-NC-NC
5962-8670403PA ACTIVE CDIP JG 8 1 TBD A42 SNPB Level-NC-NC-NC
5962-8670403VPA ACTIVE CDIP JG 8 1 TBD Call TI Level-NC-NC-NC
5962-8670403VXA ACTIVE LCCC FK 20 1 TBD Call TI Level-NC-NC-NC
5962-8670403XA ACTIVE LCCC FK 20 1 TBD POST-PLATE Level-NC-NC-NC
5962-8670404PA ACTIVE CDIP JG 8 1 TBD A42 SNPB Level-NC-NC-NC
5962-8670404VPA ACTIVE CDIP JG 8 1 TBD Call TI Level-NC-NC-NC
5962-8670404VXA ACTIVE LCCC FK 20 1 TBD Call TI Level-NC-NC-NC
5962-8670404XA ACTIVE LCCC FK 20 1 TBD POST-PLATE Level-NC-NC-NC
UC1842J ACTIVE CDIP JG 8 1 TBD A42 SNPB Level-NC-NC-NC
UC1842J883B ACTIVE CDIP JG 8 1 TBD A42 SNPB Level-NC-NC-NC
UC1842JQMLV ACTIVE CDIP JG 8 TBD Call TI Call TI
UC1842L883B ACTIVE LCCC FK 20 1 TBD POST-PLATE Level-NC-NC-NC
UC1842W ACTIVE CFP W 14 1 TBD A42 SNPB Level-NC-NC-NC
UC1843J ACTIVE CDIP JG 8 1 TBD A42 SNPB Level-NC-NC-NC
UC1843J883B ACTIVE CDIP JG 8 1 TBD A42 SNPB Level-NC-NC-NC
UC1843JQMLV ACTIVE CDIP JG 8 TBD Call TI Call TI
UC1843L ACTIVE LCCC FK 20 1 TBD POST-PLATE Level-NC-NC-NC
UC1843L883B ACTIVE LCCC FK 20 1 TBD POST-PLATE Level-NC-NC-NC
UC1843LQMLV ACTIVE LCCC FK 20 TBD Call TI Call TI
UC1843W ACTIVE CFP W 14 1 TBD A42 SNPB Level-NC-NC-NC
UC1844J ACTIVE CDIP JG 8 1 TBD A42 SNPB Level-NC-NC-NC
UC1844J883B ACTIVE CDIP JG 8 1 TBD A42 SNPB Level-NC-NC-NC
UC1844JQMLV ACTIVE CDIP JG 8 TBD Call TI Call TI
UC1844L ACTIVE LCCC FK 20 1 TBD POST-PLATE Level-NC-NC-NC
UC1844L883B ACTIVE LCCC FK 20 1 TBD POST-PLATE Level-NC-NC-NC
UC1844LQMLV ACTIVE LCCC FK 20 TBD Call TI Call TI
UC1844W ACTIVE CFP W 14 1 TBD A42 SNPB Level-NC-NC-NC
UC1845J ACTIVE CDIP JG 8 1 TBD A42 SNPB Level-NC-NC-NC
UC1845J883B ACTIVE CDIP JG 8 1 TBD A42 SNPB Level-NC-NC-NC
UC1845JQMLV ACTIVE CDIP JG 8 TBD Call TI Call TI
UC1845L ACTIVE LCCC FK 20 1 TBD POST-PLATE Level-NC-NC-NC
UC1845L883B ACTIVE LCCC FK 20 1 TBD POST-PLATE Level-NC-NC-NC
UC1845LQMLV ACTIVE LCCC FK 20 TBD Call TI Call TI
UC1845W ACTIVE CFP W 14 1 TBD A42 SNPB Level-NC-NC-NC
Addendum-Page 1

PACKAGE OPTION ADDENDUM
www.ti.com
30-Mar-2005
Orderable Device Status (1) Package
Type
Package
Drawing
Pins Package
Qty
Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
UC2842D ACTIVE SOIC D 14 50 TBD CU NIPDAU Level-1-220C-UNLIM
UC2842D8 ACTIVE SOIC D 8 75 TBD CU NIPDAU Level-2-220C-1 YEAR
UC2842D8TR ACTIVE SOIC D 8 2500 TBD CU NIPDAU Level-2-220C-1 YEAR
UC2842DR ACTIVE SOIC D 14 TBD Call TI Call TI
UC2842DTR ACTIVE SOIC D 14 2500 TBD CU NIPDAU Level-1-220C-UNLIM
UC2842DW ACTIVE SOIC DW 16 40 TBD CU NIPDAU Level-2-220C-1 YEAR
UC2842DWTR ACTIVE SOIC DW 16 2000 TBD CU NIPDAU Level-2-220C-1 YEAR
UC2842J OBSOLETE CDIP JG 8 TBD Call TI Call TI
UC2842N ACTIVE PDIP P 8 50 TBD CU NIPDAU Level-NA-NA-NA
UC2842P OBSOLETE PDIP P 8 TBD Call TI Call TI
UC2843D ACTIVE SOIC D 14 50 TBD CU NIPDAU Level-1-220C-UNLIM
UC2843D8 ACTIVE SOIC D 8 75 TBD CU NIPDAU Level-2-220C-1 YEAR
UC2843D8TR ACTIVE SOIC D 8 2500 TBD CU NIPDAU Level-2-220C-1 YEAR
UC2843DR OBSOLETE SOIC D 14 TBD Call TI Call TI
UC2843DTR ACTIVE SOIC D 14 2500 TBD CU NIPDAU Level-1-220C-UNLIM
UC2843J OBSOLETE CDIP JG 8 TBD Call TI Call TI
UC2843N ACTIVE PDIP P 8 50 TBD CU NIPDAU Level-NA-NA-NA
UC2844D ACTIVE SOIC D 14 50 TBD CU NIPDAU Level-1-220C-UNLIM
UC2844D8 ACTIVE SOIC D 8 75 TBD CU NIPDAU Level-2-220C-1 YEAR
UC2844D8TR ACTIVE SOIC D 8 2500 TBD CU NIPDAU Level-2-220C-1 YEAR
UC2844DTR ACTIVE SOIC D 14 2500 TBD CU NIPDAU Level-1-220C-UNLIM
UC2844N ACTIVE PDIP P 8 50 TBD CU NIPDAU Level-NA-NA-NA
UC2845D ACTIVE SOIC D 14 50 TBD CU NIPDAU Level-1-220C-UNLIM
UC2845D8 ACTIVE SOIC D 8 75 TBD CU NIPDAU Level-2-220C-1 YEAR
UC2845D8TR ACTIVE SOIC D 8 2500 TBD CU NIPDAU Level-2-220C-1 YEAR
UC2845DTR ACTIVE SOIC D 14 2500 TBD CU NIPDAU Level-1-220C-UNLIM
UC2845J OBSOLETE CDIP JG 8 TBD Call TI Call TI
UC2845N ACTIVE PDIP P 8 50 TBD CU NIPDAU Level-NA-NA-NA
UC3842D ACTIVE SOIC D 14 50 TBD CU NIPDAU Level-1-220C-UNLIM
UC3842D8 ACTIVE SOIC D 8 75 TBD CU NIPDAU Level-2-220C-1 YEAR
UC3842D8TR ACTIVE SOIC D 8 2500 TBD CU NIPDAU Level-2-220C-1 YEAR
UC3842DTR ACTIVE SOIC D 14 2500 TBD CU NIPDAU Level-1-220C-UNLIM
UC3842J ACTIVE CDIP JG 8 1 TBD A42 SNPB Level-NC-NC-NC
UC3842N ACTIVE PDIP P 8 50 TBD CU NIPDAU Level-NA-NA-NA
UC3842P OBSOLETE PDIP P 8 TBD Call TI Call TI
UC3843D ACTIVE SOIC D 14 50 TBD CU NIPDAU Level-1-220C-UNLIM
UC3843D8 ACTIVE SOIC D 8 75 TBD CU NIPDAU Level-2-220C-1 YEAR
UC3843D8TR ACTIVE SOIC D 8 2500 TBD CU NIPDAU Level-2-220C-1 YEAR
UC3843DTR ACTIVE SOIC D 14 2500 TBD CU NIPDAU Level-1-220C-UNLIM
UC3843J ACTIVE CDIP JG 8 1 TBD A42 SNPB Level-NC-NC-NC
UC3843N ACTIVE PDIP P 8 50 TBD CU NIPDAU Level-NA-NA-NA
UC3843P OBSOLETE PDIP P 8 TBD Call TI Call TI
UC3843QTR OBSOLETE PLCC FN 20 TBD Call TI Call TI
Addendum-Page 2

PACKAGE OPTION ADDENDUM
www.ti.com
30-Mar-2005
Orderable Device Status (1) Package
Type
Package
Drawing
Pins Package
Qty
Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
UC3844D ACTIVE SOIC D 14 50 TBD CU NIPDAU Level-1-220C-UNLIM
UC3844D8 ACTIVE SOIC D 8 75 TBD CU NIPDAU Level-2-220C-1 YEAR
UC3844D8TR ACTIVE SOIC D 8 2500 TBD CU NIPDAU Level-2-220C-1 YEAR
UC3844DTR ACTIVE SOIC D 14 2500 TBD CU NIPDAU Level-1-220C-UNLIM
UC3844J ACTIVE CDIP JG 8 1 TBD A42 SNPB Level-NC-NC-NC
UC3844N ACTIVE PDIP P 8 50 TBD CU NIPDAU Level-NA-NA-NA
UC3844P OBSOLETE PDIP P 8 TBD Call TI Call TI
UC3845D ACTIVE SOIC D 14 50 TBD CU NIPDAU Level-1-220C-UNLIM
UC3845D8 ACTIVE SOIC D 8 75 TBD CU NIPDAU Level-2-220C-1 YEAR
UC3845D8TR ACTIVE SOIC D 8 2500 TBD CU NIPDAU Level-2-220C-1 YEAR
UC3845DTR ACTIVE SOIC D 14 2500 TBD CU NIPDAU Level-1-220C-UNLIM
UC3845DTRG4 PREVIEW SOIC D 14 2500 TBD Call TI Call TI
UC3845J ACTIVE CDIP JG 8 1 TBD A42 SNPB Level-NC-NC-NC
UC3845N ACTIVE PDIP P 8 50 TBD CU NIPDAU Level-NA-NA-NA
UC3845P OBSOLETE PDIP P 8 TBD Call TI Call TI
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS) or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 3

MECHANICAL DATA
MCER001A – JANUARY 1995 – REVISED JANUARY 1997
JG (R-GDIP-T8)
CERAMIC DUAL-IN-LINE
0.400 (10,16)
0.355 (9,00)
8
5
0.280 (7,11)
0.245 (6,22)
1
4
0.065 (1,65)
0.045 (1,14)
0.063 (1,60)
0.015 (0,38)
0.020 (0,51) MIN
0.310 (7,87)
0.290 (7,37)
0.200 (5,08) MAX
Seating Plane
0.130 (3,30) MIN
0.100 (2,54)
0.023 (0,58)
0.015 (0,38)
0.014 (0,36)
0.008 (0,20)
0°–15°
4040107/C 08/96
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. This package can be hermetically sealed with a ceramic lid using glass frit.
D. Index point is provided on cap for terminal identification.
E. Falls within MIL STD 1835 GDIP1-T8
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

MECHANICAL DATA
MLCC006B – OCTOBER 1996
FK (S-CQCC-N**)
28 TERMINAL SHOWN
LEADLESS CERAMIC CHIP CARRIER
18 17
16
15
14
13
12
NO. OF
TERMINALS
**
MIN
A
MAX
MIN
B
MAX
19
11
20
0.342
(8,69)
0.358
(9,09)
0.307
(7,80)
0.358
(9,09)
A SQ
B SQ
20
21
22
23
24
25
26 27
28
1
2
3
4
10
9
8
7
6
5
28
44
52
68
84
0.442
(11,23)
0.640
(16,26)
0.739
(18,78)
0.938
(23,83)
1.141
(28,99)
0.458
(11,63)
0.660
(16,76)
0.761
(19,32)
0.962
(24,43)
1.165
(29,59)
0.406
(10,31)
0.495
(12,58)
0.495
(12,58)
0.850
(21,6)
1.047
(26,6)
0.458
(11,63)
0.560
(14,22)
0.560
(14,22)
0.858
(21,8)
1.063
(27,0)
0.020 (0,51)
0.010 (0,25)
0.080 (2,03)
0.064 (1,63)
0.020 (0,51)
0.010 (0,25)
0.055 (1,40)
0.045 (1,14)
0.045 (1,14)
0.035 (0,89)
0.028 (0,71)
0.022 (0,54)
0.050 (1,27)
0.045 (1,14)
0.035 (0,89)
4040140/ D 10/96
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. This package can be hermetically sealed with a metal lid.
D. The terminals are gold plated.
E. Falls within JEDEC MS-004
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

MECHANICAL DATA
MPDI001A – JANUARY 1995 – REVISED JUNE 1999
P (R-PDIP-T8)
PLASTIC DUAL-IN-LINE
8
0.400 (10,60)
0.355 (9,02)
5
0.260 (6,60)
0.240 (6,10)
1
4
0.070 (1,78) MAX
0.020 (0,51) MIN
0.325 (8,26)
0.300 (7,62)
0.015 (0,38)
0.200 (5,08) MAX
Gage Plane
Seating Plane
0.125 (3,18) MIN
0.010 (0,25) NOM
0.021 (0,53)
0.015 (0,38)
0.100 (2,54)
0.010 (0,25)
M
0.430 (10,92)
MAX
4040082/D 05/98
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. Falls within JEDEC MS-001
For the latest package information, go to http://www.ti.com/sc/docs/package/pkg_info.htm
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

MECHANICAL DATA
MPLC004A – OCTOBER 1994
FN (S-PQCC-J**)
20 PIN SHOWN
PLASTIC J-LEADED CHIP CARRIER
Seating Plane
0.004 (0,10)
3
D
D1
1
19
0.180 (4,57) MAX
0.120 (3,05)
0.090 (2,29)
0.020 (0,51) MIN
4
18
0.032 (0,81)
0.026 (0,66)
D2 / E2
E
E1
D2 / E2
8
14
9
13
0.050 (1,27)
0.008 (0,20) NOM
0.021 (0,53)
0.013 (0,33)
0.007 (0,18)
M
NO. OF
PINS
**
MIN
D/E
MAX
MIN
D1 / E1
MAX
MIN
D2 / E2
MAX
20
0.385 (9,78)
0.395 (10,03)
0.350 (8,89)
0.356 (9,04)
0.141 (3,58)
0.169 (4,29)
28
0.485 (12,32)
0.495 (12,57)
0.450 (11,43)
0.456 (11,58)
0.191 (4,85)
0.219 (5,56)
44
0.685 (17,40)
0.695 (17,65)
0.650 (16,51)
0.656 (16,66)
0.291 (7,39)
0.319 (8,10)
52
0.785 (19,94)
0.795 (20,19)
0.750 (19,05)
0.756 (19,20)
0.341 (8,66)
0.369 (9,37)
68
0.985 (25,02)
0.995 (25,27)
0.950 (24,13)
0.958 (24,33)
0.441 (11,20)
0.469 (11,91)
84 1.185 (30,10)
1.195 (30,35)
1.150 (29,21)
1.158 (29,41)
0.541 (13,74)
0.569 (14,45)
4040005/ B 03/95
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. Falls within JEDEC MS-018
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