PIC12F683 Data Sheet - Microchip
PIC12F683 Data Sheet - Microchip PIC12F683 Data Sheet - Microchip
PIC12F683 8.11 Comparator Voltage Reference The Comparator Voltage Reference module provides an internally generated voltage reference for the comparators. The following features are available: • Independent from Comparator operation • Two 16-level voltage ranges • Output clamped to VSS • Ratiometric with VDD The VRCON register (Register 8-3) controls the Voltage Reference module shown in Figure 8-7. 8.11.1 INDEPENDENT OPERATION The comparator voltage reference is independent of the comparator configuration. Setting the VREN bit of the VRCON register will enable the voltage reference. 8.11.2 OUTPUT VOLTAGE SELECTION The CVREF voltage reference has 2 ranges with 16 voltage levels in each range. Range selection is controlled by the VRR bit of the VRCON register. The 16 levels are set with the VR bits of the VRCON register. The CVREF output voltage is determined by the following equations: EQUATION 8-1: CVREF OUTPUT VOLTAGE VRR = 1 (low range): CVREF = (VR/24) × VDD VRR = 0 (high range): CVREF = (VDD/4) + (VR × VDD/32) The full range of VSS to VDD cannot be realized due to the construction of the module. See Figure 8-1. 8.11.3 OUTPUT CLAMPED TO VSS The CVREF output voltage can be set to Vss with no power consumption by configuring VRCON as follows: • VREN = 0 • VRR = 1 • VR = 0000 This allows the comparator to detect a zero-crossing while not consuming additional CVREF module current. 8.11.4 OUTPUT RATIOMETRIC TO VDD The comparator voltage reference is VDD derived and therefore, the CVREF output changes with fluctuations in VDD. The tested absolute accuracy of the Comparator Voltage Reference can be found in Section 15.0 “Electrical Specifications”. REGISTER 8-3: VRCON: VOLTAGE REFERENCE CONTROL REGISTER R/W-0 U-0 R/W-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 VREN — VRR — VR3 VR2 VR1 VR0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 VREN: CVREF Enable bit 1 = CVREF circuit powered on 0 = CVREF circuit powered down, no IDD drain and CVREF = VSS. bit 6 Unimplemented: Read as ‘0’ bit 5 VRR: CVREF Range Selection bit 1 = Low range 0 = High range bit 4 Unimplemented: Read as ‘0’ bit 3-0 VR: CVREF Value Selection 0 ≤ VR ≤ 15 When VRR = 1: CVREF = (VR/24) * VDD When VRR = 0: CVREF = VDD/4 + (VR/32) * VDD DS41211D-page 58 © 2007 Microchip Technology Inc.
PIC12F683 FIGURE 8-7: COMPARATOR VOLTAGE REFERENCE BLOCK DIAGRAM 16 Stages 8R R R R R VDD 8R VRR VREN CVREF to Comparator Input 16-1 Analog MUX 15 14 2 1 0 VR (1) VREN VR = 0000 VRR Note 1: Care should be taken to ensure VREF remains within the comparator Common mode input range. See Section 15.0 “Electrical Specifications” for more detail. TABLE 8-2: SUMMARY OF REGISTERS ASSOCIATED WITH THE COMPARATOR AND VOLTAGE REFERENCE MODULES Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on POR, BOR Value on all other Resets ANSEL — ADCS2 ADCS1 ADCS0 ANS3 ANS2 ANS1 ANS0 -000 1111 -000 1111 CMCON0 — COUT — CINV CIS CM2 CM1 CM0 -0-0 0000 -0-0 0000 CMCON1 — — — — — — T1GSS CMSYNC ---- --10 ---- --10 INTCON GIE PEIE T0IE INTE GPIE T0IF INTF GPIF 0000 0000 0000 000x PIE1 EEIE ADIE CCP1IE — CMIE OSFIE TMR2IE TMR1IE 000- 0000 0000 0000 PIR1 EEIF ADIF CCP1IF — CMIF OSFIF TMR2IF TMR1IF 000- 0000 000- 0000 GPIO — — GP5 GP4 GP3 GP2 GP1 GP0 --xx xxxx --uu uuuu TRISIO — — TRISIO5 TRISIO4 TRISIO3 TRISIO2 TRISIO1 TRISIO0 --11 1111 --11 1111 VRCON VREN — VRR — VR3 VR2 VR1 VR0 0-0- 0000 -0-0 0000 Legend: x = unknown, u = unchanged, - = unimplemented, read as ‘0’. Shaded cells are not used for comparator. © 2007 Microchip Technology Inc. DS41211D-page 59
- Page 9 and 10: PIC12F683 3.0 MEMORY ORGANIZATION 3
- Page 11 and 12: PIC12F683 TABLE 3-1: PIC12F683 SPEC
- Page 13 and 14: PIC12F683 3.2.2.1 STATUS Register T
- Page 15 and 16: PIC12F683 3.2.2.3 INTCON Register T
- Page 17 and 18: PIC12F683 3.2.2.5 PIR1 Register The
- Page 19 and 20: PIC12F683 3.3 PCL and PCLATH The Pr
- Page 21 and 22: PIC12F683 3.0 OSCILLATOR MODULE (WI
- Page 23 and 24: PIC12F683 3.3 Clock Source Modes Cl
- Page 25 and 26: PIC12F683 3.4.4 EXTERNAL RC MODES T
- Page 27 and 28: PIC12F683 3.5.3 LFINTOSC The Low-Fr
- Page 29 and 30: PIC12F683 3.6 Clock Switching The s
- Page 31 and 32: PIC12F683 3.8 Fail-Safe Clock Monit
- Page 33 and 34: PIC12F683 4.0 GPIO PORT There are a
- Page 35 and 36: PIC12F683 REGISTER 4-3: ANSEL: ANAL
- Page 37 and 38: PIC12F683 4.2.4 ULTRA LOW-POWER WAK
- Page 39 and 40: PIC12F683 4.2.5.2 GP1/AN1/CIN-/VREF
- Page 41 and 42: PIC12F683 4.2.5.6 GP5/T1CKI/OSC1/CL
- Page 43 and 44: PIC12F683 5.0 TIMER0 MODULE The Tim
- Page 45 and 46: PIC12F683 REGISTER 5-1: OPTION_REG:
- Page 47 and 48: PIC12F683 6.2.1 INTERNAL CLOCK SOUR
- Page 49 and 50: PIC12F683 6.11 Timer1 Control Regis
- Page 51 and 52: PIC12F683 7.0 TIMER2 MODULE The Tim
- Page 53 and 54: PIC12F683 8.0 COMPARATOR MODULE FIG
- Page 55 and 56: PIC12F683 8.3 Comparator Configurat
- Page 57 and 58: PIC12F683 8.6 Comparator Interrupt
- Page 59: PIC12F683 8.9 Comparator Gating Tim
- Page 63 and 64: PIC12F683 9.0 ANALOG-TO-DIGITAL CON
- Page 65 and 66: PIC12F683 9.1.5 INTERRUPTS The ADC
- Page 67 and 68: PIC12F683 REGISTER 9-1: ADCON0: A/D
- Page 69 and 70: PIC12F683 9.3 A/D Acquisition Requi
- Page 71 and 72: PIC12F683 TABLE 9-2: SUMMARY OF ASS
- Page 73 and 74: PIC12F683 10.0 DATA EEPROM MEMORY T
- Page 75 and 76: PIC12F683 10.2 Reading the EEPROM D
- Page 77 and 78: PIC12F683 11.0 CAPTURE/COMPARE/PWM
- Page 79 and 80: PIC12F683 11.2 Compare Mode In Comp
- Page 81 and 82: PIC12F683 11.3.1 PWM PERIOD The PWM
- Page 83 and 84: PIC12F683 TABLE 11-4: TABLE 11-5: R
- Page 85 and 86: PIC12F683 12.0 SPECIAL FEATURES OF
- Page 87 and 88: PIC12F683 12.2 Calibration Bits Bro
- Page 89 and 90: PIC12F683 12.3.4 BROWN-OUT RESET (B
- Page 91 and 92: PIC12F683 FIGURE 12-4: TIME-OUT SEQ
- Page 93 and 94: PIC12F683 TABLE 12-4: INITIALIZATIO
- Page 95 and 96: PIC12F683 12.4.2 TIMER0 INTERRUPT A
- Page 97 and 98: PIC12F683 12.5 Context Saving Durin
- Page 99 and 100: PIC12F683 REGISTER 12-2: WDTCON: WA
- Page 101 and 102: PIC12F683 FIGURE 12-10: WAKE-UP FRO
- Page 103 and 104: PIC12F683 13.0 INSTRUCTION SET SUMM
- Page 105 and 106: PIC12F683 13.2 Instruction Descript
- Page 107 and 108: PIC12F683 DECFSZ Decrement f, Skip
- Page 109 and 110: PIC12F683 RETFIE Return from Interr
<strong>PIC12F683</strong><br />
FIGURE 8-7:<br />
COMPARATOR VOLTAGE REFERENCE BLOCK DIAGRAM<br />
16 Stages<br />
8R R R R R<br />
VDD<br />
8R<br />
VRR<br />
VREN<br />
CVREF to<br />
Comparator<br />
Input<br />
16-1 Analog<br />
MUX<br />
15<br />
14<br />
2<br />
1<br />
0<br />
VR (1)<br />
VREN<br />
VR = 0000<br />
VRR<br />
Note 1:<br />
Care should be taken to ensure VREF<br />
remains within the comparator Common<br />
mode input range. See Section 15.0<br />
“Electrical Specifications” for more detail.<br />
TABLE 8-2:<br />
SUMMARY OF REGISTERS ASSOCIATED WITH THE COMPARATOR AND VOLTAGE<br />
REFERENCE MODULES<br />
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0<br />
Value on<br />
POR, BOR<br />
Value on<br />
all other<br />
Resets<br />
ANSEL — ADCS2 ADCS1 ADCS0 ANS3 ANS2 ANS1 ANS0 -000 1111 -000 1111<br />
CMCON0 — COUT — CINV CIS CM2 CM1 CM0 -0-0 0000 -0-0 0000<br />
CMCON1 — — — — — — T1GSS CMSYNC ---- --10 ---- --10<br />
INTCON GIE PEIE T0IE INTE GPIE T0IF INTF GPIF 0000 0000 0000 000x<br />
PIE1 EEIE ADIE CCP1IE — CMIE OSFIE TMR2IE TMR1IE 000- 0000 0000 0000<br />
PIR1 EEIF ADIF CCP1IF — CMIF OSFIF TMR2IF TMR1IF 000- 0000 000- 0000<br />
GPIO — — GP5 GP4 GP3 GP2 GP1 GP0 --xx xxxx --uu uuuu<br />
TRISIO — — TRISIO5 TRISIO4 TRISIO3 TRISIO2 TRISIO1 TRISIO0 --11 1111 --11 1111<br />
VRCON VREN — VRR — VR3 VR2 VR1 VR0 0-0- 0000 -0-0 0000<br />
Legend: x = unknown, u = unchanged, - = unimplemented, read as ‘0’. Shaded cells are not used for comparator.<br />
© 2007 <strong>Microchip</strong> Technology Inc. DS41211D-page 59
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