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PIC12F683 Data Sheet - Microchip

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<strong>PIC12F683</strong><br />

8.0 COMPARATOR MODULE<br />

FIGURE 8-1:<br />

SINGLE COMPARATOR<br />

Comparators are used to interface analog circuits to a<br />

digital circuit by comparing two analog voltages and<br />

providing a digital indication of their relative magnitudes.<br />

The comparators are very useful mixed signal building<br />

blocks because they provide analog functionality<br />

independent of the program execution. The analog<br />

comparator module includes the following features:<br />

• Multiple comparator configurations<br />

• Comparator output is available internally/externally<br />

• Programmable output polarity<br />

• Interrupt-on-change<br />

• Wake-up from Sleep<br />

• Timer1 gate (count enable)<br />

• Output synchronization to Timer1 clock input<br />

• Programmable voltage reference<br />

8.1 Comparator Overview<br />

The comparator is shown in Figure 8-1 along with the<br />

relationship between the analog input levels and the<br />

digital output. When the analog voltage at VIN+ is less<br />

than the analog voltage at VIN-, the output of the<br />

comparator is a digital low level. When the analog<br />

voltage at VIN+ is greater than the analog voltage at<br />

VIN-, the output of the comparator is a digital high level.<br />

Output<br />

Note:<br />

VIN+<br />

VIN-<br />

VIN-<br />

VIN+<br />

+<br />

–<br />

Output<br />

The black areas of the output of the<br />

comparator represents the uncertainty<br />

due to input offsets and response time.<br />

FIGURE 8-2:<br />

COMPARATOR OUTPUT BLOCK DIAGRAM<br />

Port Pins<br />

MULTIPLEX<br />

CINV<br />

CMSYNC<br />

0<br />

D Q<br />

1<br />

Timer1<br />

clock source (1)<br />

To Timer1 Gate<br />

To COUT pin<br />

D<br />

Q<br />

To <strong>Data</strong> Bus<br />

Q1<br />

EN<br />

RD CMCON0<br />

D<br />

Q<br />

Set CMIF bit<br />

Q3*RD CMCON0<br />

EN CL<br />

Reset<br />

Note 1: Comparator output is latched on falling edge of Timer1 clock source.<br />

2: Q1 and Q3 are phases of the four-phase system clock (FOSC).<br />

3: Q1 is held high during Sleep mode.<br />

© 2007 <strong>Microchip</strong> Technology Inc. DS41211D-page 51

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