PIC12F683 Data Sheet - Microchip

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PIC12F683 TABLE 6-1: SUMMARY OF REGISTERS ASSOCIATED WITH TIMER1 Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on POR, BOR Value on all other Resets CONFIG (1) CPD CP MCLRE PWRTE WDTE FOSC2 FOSC1 FOSC0 — — CMCON1 — — — — — — T1GSS CMSYNC ---- --10 ---- --10 INTCON GIE PEIE T0IE INTE GPIE T0IF INTF GPIF 0000 0000 0000 000x PIE1 EEIE ADIE CCP1IE — CMIE OSFIE TMR2IE TMR1IE 000- 0000 000- 0000 PIR1 EEIF ADIF CCP1IF — CMIF OSFIF TMR2IF TMR1IF 000- 0000 000- 0000 TMR1H Holding Register for the Most Significant Byte of the 16-bit TMR1 Register xxxx xxxx uuuu uuuu TMR1L Holding Register for the Least Significant Byte of the 16-bit TMR1 Register xxxx xxxx uuuu uuuu T1CON T1GINV TMR1GE T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON 0000 0000 uuuu uuuu Legend: x = unknown, u = unchanged, – = unimplemented, read as ‘0’. Shaded cells are not used by the Timer1 module. Note 1: See Configuration Word register (Register 12-1) for operation of all register bits. DS41211D-page 48 © 2007 Microchip Technology Inc.
PIC12F683 7.0 TIMER2 MODULE The Timer2 module is an 8-bit timer with the following features: • 8-bit timer register (TMR2) • 8-bit period register (PR2) • Interrupt on TMR2 match with PR2 • Software programmable prescaler (1:1, 1:4, 1:16) • Software programmable postscaler (1:1 to 1:16) See Figure 7-1 for a block diagram of Timer2. 7.1 Timer2 Operation The clock input to the Timer2 module is the system instruction clock (FOSC/4). The clock is fed into the Timer2 prescaler, which has prescale options of 1:1, 1:4 or 1:16. The output of the prescaler is then used to increment the TMR2 register. The values of TMR2 and PR2 are constantly compared to determine when they match. TMR2 will increment from 00h until it matches the value in PR2. When a match occurs, two things happen: • TMR2 is reset to 00h on the next increment cycle. • The Timer2 postscaler is incremented The match output of the Timer2/PR2 comparator is then fed into the Timer2 postscaler. The postscaler has postscale options of 1:1 to 1:16 inclusive. The output of the Timer2 postscaler is used to set the TMR2IF interrupt flag bit in the PIR1 register. The TMR2 and PR2 registers are both fully readable and writable. On any Reset, the TMR2 register is set to 00h and the PR2 register is set to FFh. Timer2 is turned on by setting the TMR2ON bit in the T2CON register to a ‘1’. Timer2 is turned off by clearing the TMR2ON bit to a ‘0’. The Timer2 prescaler is controlled by the T2CKPS bits in the T2CON register. The Timer2 postscaler is controlled by the TOUTPS bits in the T2CON register. The prescaler and postscaler counters are cleared when: • A write to TMR2 occurs. • A write to T2CON occurs. • Any device Reset occurs (Power-on Reset, MCLR Reset, Watchdog Timer Reset, or Brown-out Reset). Note: TMR2 is not cleared when T2CON is written. FIGURE 7-1: TIMER2 BLOCK DIAGRAM TMR2 Output Sets Flag bit TMR2IF FOSC/4 Prescaler 1:1, 1:4, 1:16 TMR2 Reset 2 T2CKPS Comparator PR2 EQ Postscaler 1:1 to 1:16 4 TOUTPS © 2007 Microchip Technology Inc. DS41211D-page 49
Page 1 and 2: PIC12F683 Data Sheet 8-Pin Flash-Ba
Page 3 and 4: PIC12F683 8-Pin Flash-Based, 8-Bit
Page 5 and 6: PIC12F683 Table of Contents 1.0 Dev
Page 7 and 8: PIC12F683 2.0 DEVICE OVERVIEW The P
Page 9 and 10: PIC12F683 3.0 MEMORY ORGANIZATION 3
Page 11 and 12: PIC12F683 TABLE 3-1: PIC12F683 SPEC
Page 13 and 14: PIC12F683 3.2.2.1 STATUS Register T
Page 15 and 16: PIC12F683 3.2.2.3 INTCON Register T
Page 17 and 18: PIC12F683 3.2.2.5 PIR1 Register The
Page 19 and 20: PIC12F683 3.3 PCL and PCLATH The Pr
Page 21 and 22: PIC12F683 3.0 OSCILLATOR MODULE (WI
Page 23 and 24: PIC12F683 3.3 Clock Source Modes Cl
Page 25 and 26: PIC12F683 3.4.4 EXTERNAL RC MODES T
Page 27 and 28: PIC12F683 3.5.3 LFINTOSC The Low-Fr
Page 29 and 30: PIC12F683 3.6 Clock Switching The s
Page 31 and 32: PIC12F683 3.8 Fail-Safe Clock Monit
Page 33 and 34: PIC12F683 4.0 GPIO PORT There are a
Page 35 and 36: PIC12F683 REGISTER 4-3: ANSEL: ANAL
Page 37 and 38: PIC12F683 4.2.4 ULTRA LOW-POWER WAK
Page 39 and 40: PIC12F683 4.2.5.2 GP1/AN1/CIN-/VREF
Page 41 and 42: PIC12F683 4.2.5.6 GP5/T1CKI/OSC1/CL
Page 43 and 44: PIC12F683 5.0 TIMER0 MODULE The Tim
Page 45 and 46: PIC12F683 REGISTER 5-1: OPTION_REG:
Page 47 and 48: PIC12F683 6.2.1 INTERNAL CLOCK SOUR
Page 49: PIC12F683 6.11 Timer1 Control Regis
Page 53 and 54: PIC12F683 8.0 COMPARATOR MODULE FIG
Page 55 and 56: PIC12F683 8.3 Comparator Configurat
Page 57 and 58: PIC12F683 8.6 Comparator Interrupt
Page 59 and 60: PIC12F683 8.9 Comparator Gating Tim
Page 61 and 62: PIC12F683 FIGURE 8-7: COMPARATOR VO
Page 63 and 64: PIC12F683 9.0 ANALOG-TO-DIGITAL CON
Page 65 and 66: PIC12F683 9.1.5 INTERRUPTS The ADC
Page 67 and 68: PIC12F683 REGISTER 9-1: ADCON0: A/D
Page 69 and 70: PIC12F683 9.3 A/D Acquisition Requi
Page 71 and 72: PIC12F683 TABLE 9-2: SUMMARY OF ASS
Page 73 and 74: PIC12F683 10.0 DATA EEPROM MEMORY T
Page 75 and 76: PIC12F683 10.2 Reading the EEPROM D
Page 77 and 78: PIC12F683 11.0 CAPTURE/COMPARE/PWM
Page 79 and 80: PIC12F683 11.2 Compare Mode In Comp
Page 81 and 82: PIC12F683 11.3.1 PWM PERIOD The PWM
Page 83 and 84: PIC12F683 TABLE 11-4: TABLE 11-5: R
Page 85 and 86: PIC12F683 12.0 SPECIAL FEATURES OF
Page 87 and 88: PIC12F683 12.2 Calibration Bits Bro
Page 89 and 90: PIC12F683 12.3.4 BROWN-OUT RESET (B
Page 91 and 92: PIC12F683 FIGURE 12-4: TIME-OUT SEQ
Page 93 and 94: PIC12F683 TABLE 12-4: INITIALIZATIO
Page 95 and 96: PIC12F683 12.4.2 TIMER0 INTERRUPT A
Page 97 and 98: PIC12F683 12.5 Context Saving Durin
Page 99 and 100: PIC12F683 REGISTER 12-2: WDTCON: WA
Page 101 and 102:
PIC12F683 FIGURE 12-10: WAKE-UP FRO
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PIC12F683 13.0 INSTRUCTION SET SUMM
Page 105 and 106:
PIC12F683 13.2 Instruction Descript
Page 107 and 108:
PIC12F683 DECFSZ Decrement f, Skip
Page 109 and 110:
PIC12F683 RETFIE Return from Interr
Page 111 and 112:
PIC12F683 SUBWF Subtract W from f S
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PIC12F683 14.0 DEVELOPMENT SUPPORT
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PIC12F683 14.7 MPLAB ICE 2000 High-
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PIC12F683 15.0 ELECTRICAL SPECIFICA
Page 119 and 120:
PIC12F683 15.1 DC Characteristics:
Page 121 and 122:
Page 123 and 124:
Page 125 and 126:
PIC12F683 15.6 Thermal Consideratio
Page 127 and 128:
PIC12F683 15.8 AC Characteristics:
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PIC12F683 FIGURE 15-5: CLKOUT AND I
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PIC12F683 TABLE 15-4: RESET, WATCHD
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PIC12F683 FIGURE 15-9: CAPTURE/COMP
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PIC12F683 TABLE 15-9: PIC12F683 A/D
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PIC12F683 FIGURE 15-10: PIC12F683 A
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PIC12F683 16.0 DC AND AC CHARACTERI
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PIC12F683 FIGURE 16-4: 5.0 MAXIMUM
Page 143 and 144:
PIC12F683 FIGURE 16-8: MAXIMUM IDD
Page 145 and 146:
PIC12F683 FIGURE 16-12: MAXIMUM IDD
Page 147 and 148:
PIC12F683 FIGURE 16-16: BOR IPD vs.
Page 149 and 150:
PIC12F683 FIGURE 16-20: WDT PERIOD
Page 151 and 152:
PIC12F683 FIGURE 16-24: VOL vs. IOL
Page 153 and 154:
PIC12F683 FIGURE 16-28: SCHMITT TRI
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PIC12F683 FIGURE 16-32: LFINTOSC FR
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PIC12F683 FIGURE 16-36: MINIMUM HFI
Page 159 and 160:
PIC12F683 FIGURE 16-40: TYPICAL HFI
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PIC12F683 17.0 PACKAGING INFORMATIO
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PIC12F683 8-Lead Plastic Small Outl
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PIC12F683 8-Lead Plastic Dual Flat,
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PIC12F683 APPENDIX A: Revision A Th
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PIC12F683 INDEX A A/D Specification
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PIC12F683 SUBLW ...................
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PIC12F683 THE MICROCHIP WEB SITE Mi
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PIC12F683 PRODUCT IDENTIFICATION SY
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