PIC12F683 Data Sheet - Microchip

More documents

Recommendations

Info

PIC12F683 4.2.5.4 GP3/MCLR/VPP Figure 4-4 shows the diagram for this pin. The GP3 pin is configurable to function as one of the following: • a general purpose input • as Master Clear Reset with weak pull-up FIGURE 4-4: BLOCK DIAGRAM OF GP3 VDD 4.2.5.5 GP4/AN3/T1G/OSC2/CLKOUT Figure 4-5 shows the diagram for this pin. The GP4 pin is configurable to function as one of the following: • a general purpose I/O • an analog input for the ADC • a Timer1 gate input • a crystal/resonator connection • a clock output MCLRE Weak FIGURE 4-5: BLOCK DIAGRAM OF GP4 Data Bus RD TRISIO RD GPIO Reset VSS MCLRE MCLRE VSS Input pin Data Bus WR WPU D CK Q Q Analog Input Mode CLK (1) Modes VDD Weak WR IOC RD IOC D Interrupt-onchange CK Q Q Q D EN Q D EN RD GPIO Q3 RD WPU WR GPIO WR TRISIO RD TRISIO RD GPIO D CK D CK Q Q Q Q OSC1 FOSC/4 GPPU Oscillator Circuit CLKOUT Enable 1 0 CLKOUT Enable INTOSC/ RC/EC (2) CLKOUT Enable Analog Input Mode VDD I/O pin VSS D Q WR IOC RD IOC CK Q Q Q D EN D Q3 Interrupt-onchange To T1G To A/D Converter EN RD GPIO Note 1: CLK modes are XT, HS, LP, optional LP oscillator and CLKOUT Enable. 2: With CLKOUT option. DS41211D-page 38 © 2007 Microchip Technology Inc.
PIC12F683 4.2.5.6 GP5/T1CKI/OSC1/CLKIN FIGURE 4-6: BLOCK DIAGRAM OF GP5 Figure 4-6 shows the diagram for this pin. The GP5 pin is configurable to function as one of the following: • a general purpose I/O • a Timer1 clock input • a crystal/resonator connection • a clock input Data Bus WR WPU RD WPU D D CK Q Q Q INTOSC Mode OSC2 GPPU TMR1LPEN (1) Oscillator Circuit VDD Weak VDD WR GPIO CK Q D Q I/O pin WR TRISIO CK Q VSS RD TRISIO INTOSC Mode RD GPIO (1) D Q WR IOC RD IOC CK Q Q D EN Q3 Q D Interrupt-onchange EN RD GPIO TABLE 4-1: SUMMARY OF REGISTERS ASSOCIATED WITH GPIO To Timer1 or CLKGEN Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Note 1: Timer1 LP oscillator enabled. 2: When using Timer1 with LP oscillator, the Schmitt Trigger is bypassed. Value on POR, BOR Value on all other Resets ANSEL — ADCS2 ADCS1 ADCS0 ANS3 ANS2 ANS1 ANS0 -000 1111 -000 1111 CCP1CON — — DC1B1 DC1B0 CCP1M3 CCP1M2 CCP1M1 CCP1M0 --00 0000 --00 0000 CMCON0 — COUT — CINV CIS CM2 CM1 CM0 -0-0 0000 -0-0 0000 PCON — — ULPWUE SBOREN — — POR BOR --01 --qq --0u --uu INTCON GIE PEIE T0IE INTE GPIE T0IF INTF GPIF 0000 0000 0000 000x IOC — — IOC5 IOC4 IOC3 IOC2 IOC1 IOC0 --00 0000 --00 0000 OPTION_REG GPPU INTEDG T0CS T0SE PSA PS2 PS1 PS0 1111 1111 1111 1111 GPIO — — GP5 GP4 GP3 GP2 GP1 GP0 --xx xxxx --x0 x000 T1CON T1GINV TMR1GE T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON 0000 0000 0000 0000 TRISIO — — TRISIO5 TRISIO4 TRISIO3 TRISIO2 TRISIO1 TRISIO0 --11 1111 --11 1111 WPU — — WPU5 WPU4 — WPU2 WPU1 WPU0 --11 -111 --11 -111 Legend: x = unknown, u = unchanged, – = unimplemented locations read as ‘0’. Shaded cells are not used by GPIO. © 2007 Microchip Technology Inc. DS41211D-page 39
Page 1 and 2: PIC12F683 Data Sheet 8-Pin Flash-Ba
Page 3 and 4: PIC12F683 8-Pin Flash-Based, 8-Bit
Page 5 and 6: PIC12F683 Table of Contents 1.0 Dev
Page 7 and 8: PIC12F683 2.0 DEVICE OVERVIEW The P
Page 9 and 10: PIC12F683 3.0 MEMORY ORGANIZATION 3
Page 11 and 12: PIC12F683 TABLE 3-1: PIC12F683 SPEC
Page 13 and 14: PIC12F683 3.2.2.1 STATUS Register T
Page 15 and 16: PIC12F683 3.2.2.3 INTCON Register T
Page 17 and 18: PIC12F683 3.2.2.5 PIR1 Register The
Page 19 and 20: PIC12F683 3.3 PCL and PCLATH The Pr
Page 21 and 22: PIC12F683 3.0 OSCILLATOR MODULE (WI
Page 23 and 24: PIC12F683 3.3 Clock Source Modes Cl
Page 25 and 26: PIC12F683 3.4.4 EXTERNAL RC MODES T
Page 27 and 28: PIC12F683 3.5.3 LFINTOSC The Low-Fr
Page 29 and 30: PIC12F683 3.6 Clock Switching The s
Page 31 and 32: PIC12F683 3.8 Fail-Safe Clock Monit
Page 33 and 34: PIC12F683 4.0 GPIO PORT There are a
Page 35 and 36: PIC12F683 REGISTER 4-3: ANSEL: ANAL
Page 37 and 38: PIC12F683 4.2.4 ULTRA LOW-POWER WAK
Page 39: PIC12F683 4.2.5.2 GP1/AN1/CIN-/VREF
Page 43 and 44: PIC12F683 5.0 TIMER0 MODULE The Tim
Page 45 and 46: PIC12F683 REGISTER 5-1: OPTION_REG:
Page 47 and 48: PIC12F683 6.2.1 INTERNAL CLOCK SOUR
Page 49 and 50: PIC12F683 6.11 Timer1 Control Regis
Page 51 and 52: PIC12F683 7.0 TIMER2 MODULE The Tim
Page 53 and 54: PIC12F683 8.0 COMPARATOR MODULE FIG
Page 55 and 56: PIC12F683 8.3 Comparator Configurat
Page 57 and 58: PIC12F683 8.6 Comparator Interrupt
Page 59 and 60: PIC12F683 8.9 Comparator Gating Tim
Page 61 and 62: PIC12F683 FIGURE 8-7: COMPARATOR VO
Page 63 and 64: PIC12F683 9.0 ANALOG-TO-DIGITAL CON
Page 65 and 66: PIC12F683 9.1.5 INTERRUPTS The ADC
Page 67 and 68: PIC12F683 REGISTER 9-1: ADCON0: A/D
Page 69 and 70: PIC12F683 9.3 A/D Acquisition Requi
Page 71 and 72: PIC12F683 TABLE 9-2: SUMMARY OF ASS
Page 73 and 74: PIC12F683 10.0 DATA EEPROM MEMORY T
Page 75 and 76: PIC12F683 10.2 Reading the EEPROM D
Page 77 and 78: PIC12F683 11.0 CAPTURE/COMPARE/PWM
Page 79 and 80: PIC12F683 11.2 Compare Mode In Comp
Page 81 and 82: PIC12F683 11.3.1 PWM PERIOD The PWM
Page 83 and 84: PIC12F683 TABLE 11-4: TABLE 11-5: R
Page 85 and 86: PIC12F683 12.0 SPECIAL FEATURES OF
Page 87 and 88: PIC12F683 12.2 Calibration Bits Bro
Page 89 and 90: PIC12F683 12.3.4 BROWN-OUT RESET (B
Page 91 and 92:
PIC12F683 FIGURE 12-4: TIME-OUT SEQ
Page 93 and 94:
PIC12F683 TABLE 12-4: INITIALIZATIO
Page 95 and 96:
PIC12F683 12.4.2 TIMER0 INTERRUPT A
Page 97 and 98:
PIC12F683 12.5 Context Saving Durin
Page 99 and 100:
PIC12F683 REGISTER 12-2: WDTCON: WA
Page 101 and 102:
PIC12F683 FIGURE 12-10: WAKE-UP FRO
Page 103 and 104:
PIC12F683 13.0 INSTRUCTION SET SUMM
Page 105 and 106:
PIC12F683 13.2 Instruction Descript
Page 107 and 108:
PIC12F683 DECFSZ Decrement f, Skip
Page 109 and 110:
PIC12F683 RETFIE Return from Interr
Page 111 and 112:
PIC12F683 SUBWF Subtract W from f S
Page 113 and 114:
PIC12F683 14.0 DEVELOPMENT SUPPORT
Page 115 and 116:
PIC12F683 14.7 MPLAB ICE 2000 High-
Page 117 and 118:
PIC12F683 15.0 ELECTRICAL SPECIFICA
Page 119 and 120:
PIC12F683 15.1 DC Characteristics:
Page 121 and 122:
Page 123 and 124:
Page 125 and 126:
PIC12F683 15.6 Thermal Consideratio
Page 127 and 128:
PIC12F683 15.8 AC Characteristics:
Page 129 and 130:
PIC12F683 FIGURE 15-5: CLKOUT AND I
Page 131 and 132:
PIC12F683 TABLE 15-4: RESET, WATCHD
Page 133 and 134:
PIC12F683 FIGURE 15-9: CAPTURE/COMP
Page 135 and 136:
PIC12F683 TABLE 15-9: PIC12F683 A/D
Page 137 and 138:
PIC12F683 FIGURE 15-10: PIC12F683 A
Page 139 and 140:
PIC12F683 16.0 DC AND AC CHARACTERI
Page 141 and 142:
PIC12F683 FIGURE 16-4: 5.0 MAXIMUM
Page 143 and 144:
PIC12F683 FIGURE 16-8: MAXIMUM IDD
Page 145 and 146:
PIC12F683 FIGURE 16-12: MAXIMUM IDD
Page 147 and 148:
PIC12F683 FIGURE 16-16: BOR IPD vs.
Page 149 and 150:
PIC12F683 FIGURE 16-20: WDT PERIOD
Page 151 and 152:
PIC12F683 FIGURE 16-24: VOL vs. IOL
Page 153 and 154:
PIC12F683 FIGURE 16-28: SCHMITT TRI
Page 155 and 156:
PIC12F683 FIGURE 16-32: LFINTOSC FR
Page 157 and 158:
PIC12F683 FIGURE 16-36: MINIMUM HFI
Page 159 and 160:
PIC12F683 FIGURE 16-40: TYPICAL HFI
Page 161 and 162:
PIC12F683 17.0 PACKAGING INFORMATIO
Page 163 and 164:
PIC12F683 8-Lead Plastic Small Outl
Page 165 and 166:
PIC12F683 8-Lead Plastic Dual Flat,
Page 167 and 168:
PIC12F683 APPENDIX A: Revision A Th
Page 169 and 170:
PIC12F683 INDEX A A/D Specification
Page 171 and 172:
PIC12F683 SUBLW ...................
Page 173 and 174:
PIC12F683 THE MICROCHIP WEB SITE Mi
Page 175 and 176:
PIC12F683 PRODUCT IDENTIFICATION SY
show all

PIC12F683 Data Sheet - Microchip

Create successful ePaper yourself

Delete template?

Save as template?