PIC12F683 Data Sheet - Microchip
PIC12F683 Data Sheet - Microchip PIC12F683 Data Sheet - Microchip
PIC12F683 3.2.2.4 PIE1 Register The PIE1 register contains the interrupt enable bits, as shown in Register 3-4. Note: Bit PEIE of the INTCON register must be set to enable any peripheral interrupt. REGISTER 3-4: PIE1: PERIPHERAL INTERRUPT ENABLE REGISTER 1 R/W-0 R/W-0 R/W-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 EEIE ADIE CCP1IE — CMIE OSFIE TMR2IE TMR1IE bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 bit 6 EEIE: EE Write Complete Interrupt Enable bit 1 = Enables the EE write complete interrupt 0 = Disables the EE write complete interrupt ADIE: A/D Converter (ADC) Interrupt Enable bit 1 = Enables the ADC interrupt 0 = Disables the ADC interrupt bit 5 CCP1IE: CCP1 Interrupt Enable bit 1 = Enables the CCP1 interrupt 0 = Disables the CCP1 interrupt bit 4 Unimplemented: Read as ‘0’ bit 3 bit 2 bit 1 bit 0 CMIE: Comparator Interrupt Enable bit 1 = Enables the Comparator 1 interrupt 0 = Disables the Comparator 1 interrupt OSFIE: Oscillator Fail Interrupt Enable bit 1 = Enables the oscillator fail interrupt 0 = Disables the oscillator fail interrupt TMR2IE: Timer2 to PR2 Match Interrupt Enable bit 1 = Enables the Timer2 to PR2 match interrupt 0 = Disables the Timer2 to PR2 match interrupt TMR1IE: Timer1 Overflow Interrupt Enable bit 1 = Enables the Timer1 overflow interrupt 0 = Disables the Timer1 overflow interrupt DS41211D-page 14 © 2007 Microchip Technology Inc.
PIC12F683 3.2.2.5 PIR1 Register The PIR1 register contains the interrupt flag bits, as shown in Register 3-5. Note: Interrupt flag bits are set when an interrupt condition occurs, regardless of the state of its corresponding enable bit or the global enable bit, GIE of the INTCON register. User software should ensure the appropriate interrupt flag bits are clear prior to enabling an interrupt. REGISTER 3-5: PIR1: PERIPHERAL INTERRUPT REQUEST REGISTER 1 R/W-0 R/W-0 R/W-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 EEIF ADIF CCP1IF — CMIF OSFIF TMR2IF TMR1IF bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 bit 6 EEIF: EEPROM Write Operation Interrupt Flag bit 1 = The write operation completed (must be cleared in software) 0 = The write operation has not completed or has not been started ADIF: A/D Interrupt Flag bit 1 = A/D conversion complete 0 = A/D conversion has not completed or has not been started bit 5 CCP1IF: CCP1 Interrupt Flag bit Capture mode: 1 = A TMR1 register capture occurred (must be cleared in software) 0 = No TMR1 register capture occurred Compare mode: 1 = A TMR1 register compare match occurred (must be cleared in software) 0 = No TMR1 register compare match occurred PWM mode: Unused in this mode bit 4 Unimplemented: Read as ‘0’ bit 3 bit 2 bit 1 bit 0 CMIF: Comparator Interrupt Flag bit 1 = Comparator 1 output has changed (must be cleared in software) 0 = Comparator 1 output has not changed OSFIF: Oscillator Fail Interrupt Flag bit 1 = System oscillator failed, clock input has changed to INTOSC (must be cleared in software) 0 = System clock operating TMR2IF: Timer2 to PR2 Match Interrupt Flag bit 1 = Timer2 to PR2 match occurred (must be cleared in software) 0 = Timer2 to PR2 match has not occurred TMR1IF: Timer1 Overflow Interrupt Flag bit 1 = Timer1 register overflowed (must be cleared in software) 0 = Timer1 has not overflowed © 2007 Microchip Technology Inc. DS41211D-page 15
- Page 1 and 2: PIC12F683 Data Sheet 8-Pin Flash-Ba
- Page 3 and 4: PIC12F683 8-Pin Flash-Based, 8-Bit
- Page 5 and 6: PIC12F683 Table of Contents 1.0 Dev
- Page 7 and 8: PIC12F683 2.0 DEVICE OVERVIEW The P
- Page 9 and 10: PIC12F683 3.0 MEMORY ORGANIZATION 3
- Page 11 and 12: PIC12F683 TABLE 3-1: PIC12F683 SPEC
- Page 13 and 14: PIC12F683 3.2.2.1 STATUS Register T
- Page 15: PIC12F683 3.2.2.3 INTCON Register T
- Page 19 and 20: PIC12F683 3.3 PCL and PCLATH The Pr
- Page 21 and 22: PIC12F683 3.0 OSCILLATOR MODULE (WI
- Page 23 and 24: PIC12F683 3.3 Clock Source Modes Cl
- Page 25 and 26: PIC12F683 3.4.4 EXTERNAL RC MODES T
- Page 27 and 28: PIC12F683 3.5.3 LFINTOSC The Low-Fr
- Page 29 and 30: PIC12F683 3.6 Clock Switching The s
- Page 31 and 32: PIC12F683 3.8 Fail-Safe Clock Monit
- Page 33 and 34: PIC12F683 4.0 GPIO PORT There are a
- Page 35 and 36: PIC12F683 REGISTER 4-3: ANSEL: ANAL
- Page 37 and 38: PIC12F683 4.2.4 ULTRA LOW-POWER WAK
- Page 39 and 40: PIC12F683 4.2.5.2 GP1/AN1/CIN-/VREF
- Page 41 and 42: PIC12F683 4.2.5.6 GP5/T1CKI/OSC1/CL
- Page 43 and 44: PIC12F683 5.0 TIMER0 MODULE The Tim
- Page 45 and 46: PIC12F683 REGISTER 5-1: OPTION_REG:
- Page 47 and 48: PIC12F683 6.2.1 INTERNAL CLOCK SOUR
- Page 49 and 50: PIC12F683 6.11 Timer1 Control Regis
- Page 51 and 52: PIC12F683 7.0 TIMER2 MODULE The Tim
- Page 53 and 54: PIC12F683 8.0 COMPARATOR MODULE FIG
- Page 55 and 56: PIC12F683 8.3 Comparator Configurat
- Page 57 and 58: PIC12F683 8.6 Comparator Interrupt
- Page 59 and 60: PIC12F683 8.9 Comparator Gating Tim
- Page 61 and 62: PIC12F683 FIGURE 8-7: COMPARATOR VO
- Page 63 and 64: PIC12F683 9.0 ANALOG-TO-DIGITAL CON
- Page 65 and 66: PIC12F683 9.1.5 INTERRUPTS The ADC
<strong>PIC12F683</strong><br />
3.2.2.5 PIR1 Register<br />
The PIR1 register contains the interrupt flag bits, as<br />
shown in Register 3-5.<br />
Note:<br />
Interrupt flag bits are set when an interrupt<br />
condition occurs, regardless of the state of<br />
its corresponding enable bit or the global<br />
enable bit, GIE of the INTCON register.<br />
User software should ensure the appropriate<br />
interrupt flag bits are clear prior to<br />
enabling an interrupt.<br />
REGISTER 3-5: PIR1: PERIPHERAL INTERRUPT REQUEST REGISTER 1<br />
R/W-0 R/W-0 R/W-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0<br />
EEIF ADIF CCP1IF — CMIF OSFIF TMR2IF TMR1IF<br />
bit 7 bit 0<br />
Legend:<br />
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’<br />
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown<br />
bit 7<br />
bit 6<br />
EEIF: EEPROM Write Operation Interrupt Flag bit<br />
1 = The write operation completed (must be cleared in software)<br />
0 = The write operation has not completed or has not been started<br />
ADIF: A/D Interrupt Flag bit<br />
1 = A/D conversion complete<br />
0 = A/D conversion has not completed or has not been started<br />
bit 5<br />
CCP1IF: CCP1 Interrupt Flag bit<br />
Capture mode:<br />
1 = A TMR1 register capture occurred (must be cleared in software)<br />
0 = No TMR1 register capture occurred<br />
Compare mode:<br />
1 = A TMR1 register compare match occurred (must be cleared in software)<br />
0 = No TMR1 register compare match occurred<br />
PWM mode:<br />
Unused in this mode<br />
bit 4 Unimplemented: Read as ‘0’<br />
bit 3<br />
bit 2<br />
bit 1<br />
bit 0<br />
CMIF: Comparator Interrupt Flag bit<br />
1 = Comparator 1 output has changed (must be cleared in software)<br />
0 = Comparator 1 output has not changed<br />
OSFIF: Oscillator Fail Interrupt Flag bit<br />
1 = System oscillator failed, clock input has changed to INTOSC (must be cleared in software)<br />
0 = System clock operating<br />
TMR2IF: Timer2 to PR2 Match Interrupt Flag bit<br />
1 = Timer2 to PR2 match occurred (must be cleared in software)<br />
0 = Timer2 to PR2 match has not occurred<br />
TMR1IF: Timer1 Overflow Interrupt Flag bit<br />
1 = Timer1 register overflowed (must be cleared in software)<br />
0 = Timer1 has not overflowed<br />
© 2007 <strong>Microchip</strong> Technology Inc. DS41211D-page 15
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