PIC12F683 Data Sheet - Microchip
PIC12F683 Data Sheet - Microchip PIC12F683 Data Sheet - Microchip
PIC12F683 3.2.1 GENERAL PURPOSE REGISTER FILE The register file is organized as 128 x 8 in the PIC12F683. Each register is accessed, either directly or indirectly, through the File Select Register FSR (see Section 3.4 “Indirect Addressing, INDF and FSR Registers”). 3.2.2 SPECIAL FUNCTION REGISTERS The Special Function Registers are registers used by the CPU and peripheral functions for controlling the desired operation of the device (see Table 3-1). These registers are static RAM. The special registers can be classified into two sets: core and peripheral. The Special Function Registers associated with the “core” are described in this section. Those related to the operation of the peripheral features are described in the section of that peripheral feature. FIGURE 3-2: Indirect addr. (1) TMR0 PCL STATUS FSR GPIO PCLATH INTCON PIR1 TMR1L TMR1H T1CON TMR2 T2CON CCPR1L CCPR1H CCP1CON WDTCON CMCON0 CMCON1 ADRESH ADCON0 General Purpose Registers 96 Bytes DATA MEMORY MAP OF THE PIC12F683 File Address 00h 01h 02h 03h 04h 05h 06h 07h 08h 09h 0Ah 0Bh 0Ch 0Dh 0Eh 0Fh 10h 11h 12h 13h 14h 15h 16h 17h 18h 19h 1Ah 1Bh 1Ch 1Dh 1Eh 1Fh 20h Indirect addr. (1) OPTION_REG PCL STATUS FSR TRISIO PCLATH INTCON PIE1 PCON OSCCON OSCTUNE PR2 WPU IOC VRCON EEDAT EEADR EECON1 EECON2 (1) ADRESL ANSEL General Purpose Registers 32 Bytes File Address 80h 81h 82h 83h 84h 85h 86h 87h 88h 89h 8Ah 8Bh 8Ch 8Dh 8Eh 8Fh 90h 91h 92h 93h 94h 95h 96h 97h 98h 99h 9Ah 9Bh 9Ch 9Dh 9Eh 9Fh A0h BFh C0h BANK 0 7Fh Accesses 70h-7Fh BANK 1 EFh F0h FFh Unimplemented data memory locations, read as ‘0’. Note 1: Not a physical register. DS41211D-page 8 © 2007 Microchip Technology Inc.
PIC12F683 TABLE 3-1: PIC12F683 SPECIAL REGISTERS SUMMARY BANK 0 Addr Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on POR, BOR Page Bank 0 00h INDF Addressing this location uses contents of FSR to address data memory (not a physical register) xxxx xxxx 17, 90 01h TMR0 Timer0 Module Register xxxx xxxx 41, 90 02h PCL Program Counter’s (PC) Least Significant Byte 0000 0000 17, 90 03h STATUS IRP (1) RP1 (1) RP0 TO PD Z DC C 0001 1xxx 11, 90 04h FSR Indirect Data Memory Address Pointer xxxx xxxx 17, 90 05h GPIO — — GP5 GP4 GP3 GP2 GP1 GP0 --xx xxxx 31, 90 06h — Unimplemented — — 07h — Unimplemented — — 08h — Unimplemented — — 09h — Unimplemented — — 0Ah PCLATH — — — Write Buffer for upper 5 bits of Program Counter ---0 0000 17, 90 0Bh INTCON GIE PEIE T0IE INTE GPIE T0IF INTF GPIF 0000 0000 13, 90 0Ch PIR1 EEIF ADIF CCP1IF — CMIF OSFIF TMR2IF TMR1IF 000- 0000 15, 90 0Dh — Unimplemented — — 0Eh TMR1L Holding Register for the Least Significant Byte of the 16-bit TMR1 xxxx xxxx 44, 90 0Fh TMR1H Holding Register for the Most Significant Byte of the 16-bit TMR1 xxxx xxxx 44, 90 10h T1CON T1GINV TMR1GE T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON 0000 0000 47, 90 11h TMR2 Timer2 Module Register 0000 0000 49, 90 12h T2CON — TOUTPS3 TOUTPS2 TOUTPS1 TOUTPS0 TMR2ON T2CKPS1 T2CKPS0 -000 0000 50, 90 13h CCPR1L Capture/Compare/PWM Register 1 Low Byte xxxx xxxx 76, 90 14h CCPR1H Capture/Compare/PWM Register 1 High Byte xxxx xxxx 76, 90 15h CCP1CON — — DC1B1 DC1B0 CCP1M3 CCP1M2 CCP1M1 CCP1M0 --00 0000 75, 90 16h — Unimplemented — — 17h — Unimplemented — — 18h WDTCON — — — WDTPS3 WDTPS2 WDTPS1 WDTPS0 SWDTEN ---0 1000 97, 90 19h CMCON0 — COUT — CINV CIS CM2 CM1 CM0 -0-0 0000 56, 90 1Ah CMCON1 — — — — — — T1GSS CMSYNC ---- --10 57, 90 1Bh — Unimplemented — — 1Ch — Unimplemented — — 1Dh — Unimplemented — — 1Eh ADRESH Most Significant 8 bits of the left shifted A/D result or 2 bits of right shifted result xxxx xxxx 61,90 1Fh ADCON0 ADFM VCFG — — CHS1 CHS0 GO/DONE ADON 00-- 0000 65,90 Legend: – = unimplemented locations read as ‘0’, u = unchanged, x = unknown, q = value depends on condition, shaded = unimplemented Note 1: IRP and RP1 bits are reserved, always maintain these bits clear. © 2007 Microchip Technology Inc. DS41211D-page 9
- Page 1 and 2: PIC12F683 Data Sheet 8-Pin Flash-Ba
- Page 3 and 4: PIC12F683 8-Pin Flash-Based, 8-Bit
- Page 5 and 6: PIC12F683 Table of Contents 1.0 Dev
- Page 7 and 8: PIC12F683 2.0 DEVICE OVERVIEW The P
- Page 9: PIC12F683 3.0 MEMORY ORGANIZATION 3
- Page 13 and 14: PIC12F683 3.2.2.1 STATUS Register T
- Page 15 and 16: PIC12F683 3.2.2.3 INTCON Register T
- Page 17 and 18: PIC12F683 3.2.2.5 PIR1 Register The
- Page 19 and 20: PIC12F683 3.3 PCL and PCLATH The Pr
- Page 21 and 22: PIC12F683 3.0 OSCILLATOR MODULE (WI
- Page 23 and 24: PIC12F683 3.3 Clock Source Modes Cl
- Page 25 and 26: PIC12F683 3.4.4 EXTERNAL RC MODES T
- Page 27 and 28: PIC12F683 3.5.3 LFINTOSC The Low-Fr
- Page 29 and 30: PIC12F683 3.6 Clock Switching The s
- Page 31 and 32: PIC12F683 3.8 Fail-Safe Clock Monit
- Page 33 and 34: PIC12F683 4.0 GPIO PORT There are a
- Page 35 and 36: PIC12F683 REGISTER 4-3: ANSEL: ANAL
- Page 37 and 38: PIC12F683 4.2.4 ULTRA LOW-POWER WAK
- Page 39 and 40: PIC12F683 4.2.5.2 GP1/AN1/CIN-/VREF
- Page 41 and 42: PIC12F683 4.2.5.6 GP5/T1CKI/OSC1/CL
- Page 43 and 44: PIC12F683 5.0 TIMER0 MODULE The Tim
- Page 45 and 46: PIC12F683 REGISTER 5-1: OPTION_REG:
- Page 47 and 48: PIC12F683 6.2.1 INTERNAL CLOCK SOUR
- Page 49 and 50: PIC12F683 6.11 Timer1 Control Regis
- Page 51 and 52: PIC12F683 7.0 TIMER2 MODULE The Tim
- Page 53 and 54: PIC12F683 8.0 COMPARATOR MODULE FIG
- Page 55 and 56: PIC12F683 8.3 Comparator Configurat
- Page 57 and 58: PIC12F683 8.6 Comparator Interrupt
- Page 59 and 60: PIC12F683 8.9 Comparator Gating Tim
<strong>PIC12F683</strong><br />
TABLE 3-1: <strong>PIC12F683</strong> SPECIAL REGISTERS SUMMARY BANK 0<br />
Addr Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0<br />
Value on<br />
POR, BOR<br />
Page<br />
Bank 0<br />
00h INDF Addressing this location uses contents of FSR to address data memory (not a physical register) xxxx xxxx 17, 90<br />
01h TMR0 Timer0 Module Register xxxx xxxx 41, 90<br />
02h PCL Program Counter’s (PC) Least Significant Byte 0000 0000 17, 90<br />
03h STATUS IRP (1) RP1 (1) RP0 TO PD Z DC C 0001 1xxx 11, 90<br />
04h FSR Indirect <strong>Data</strong> Memory Address Pointer xxxx xxxx 17, 90<br />
05h GPIO — — GP5 GP4 GP3 GP2 GP1 GP0 --xx xxxx 31, 90<br />
06h — Unimplemented — —<br />
07h — Unimplemented — —<br />
08h — Unimplemented — —<br />
09h — Unimplemented — —<br />
0Ah PCLATH — — — Write Buffer for upper 5 bits of Program Counter ---0 0000 17, 90<br />
0Bh INTCON GIE PEIE T0IE INTE GPIE T0IF INTF GPIF 0000 0000 13, 90<br />
0Ch PIR1 EEIF ADIF CCP1IF — CMIF OSFIF TMR2IF TMR1IF 000- 0000 15, 90<br />
0Dh — Unimplemented — —<br />
0Eh TMR1L Holding Register for the Least Significant Byte of the 16-bit TMR1 xxxx xxxx 44, 90<br />
0Fh TMR1H Holding Register for the Most Significant Byte of the 16-bit TMR1 xxxx xxxx 44, 90<br />
10h T1CON T1GINV TMR1GE T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON 0000 0000 47, 90<br />
11h TMR2 Timer2 Module Register 0000 0000 49, 90<br />
12h T2CON — TOUTPS3 TOUTPS2 TOUTPS1 TOUTPS0 TMR2ON T2CKPS1 T2CKPS0 -000 0000 50, 90<br />
13h CCPR1L Capture/Compare/PWM Register 1 Low Byte xxxx xxxx 76, 90<br />
14h CCPR1H Capture/Compare/PWM Register 1 High Byte xxxx xxxx 76, 90<br />
15h CCP1CON — — DC1B1 DC1B0 CCP1M3 CCP1M2 CCP1M1 CCP1M0 --00 0000 75, 90<br />
16h — Unimplemented — —<br />
17h — Unimplemented — —<br />
18h WDTCON — — — WDTPS3 WDTPS2 WDTPS1 WDTPS0 SWDTEN ---0 1000 97, 90<br />
19h CMCON0 — COUT — CINV CIS CM2 CM1 CM0 -0-0 0000 56, 90<br />
1Ah CMCON1 — — — — — — T1GSS CMSYNC ---- --10 57, 90<br />
1Bh — Unimplemented — —<br />
1Ch — Unimplemented — —<br />
1Dh — Unimplemented — —<br />
1Eh ADRESH Most Significant 8 bits of the left shifted A/D result or 2 bits of right shifted result xxxx xxxx 61,90<br />
1Fh ADCON0 ADFM VCFG — — CHS1 CHS0 GO/DONE ADON 00-- 0000 65,90<br />
Legend: – = unimplemented locations read as ‘0’, u = unchanged, x = unknown, q = value depends on condition,<br />
shaded = unimplemented<br />
Note 1: IRP and RP1 bits are reserved, always maintain these bits clear.<br />
© 2007 <strong>Microchip</strong> Technology Inc. DS41211D-page 9
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