Overview of Gigabit Ethernet Transceiver IC Design

Overview of Gigabit Ethernet 

Transceiver IC Design 

國立台灣大學電機系 

主講人 : 吳安宇 

清華大學積體電路中心演講 

09/13/2002 

清華大學積體電路中心演講 pp. 1 

Outline 


Gigabit Ethernet Channel (CAT 5 UTP Cable) 

1000BASE-T Transceiver 

Receiver Design Issues 

Research Results in NTUEE 

References 

清華大學積體電路中心演講 pp. 2



Target Market 

70% of installed UTP is CAT 5. 

CAT 5 installed footage is growing 30% annually. 


Relationship between Standard 

Families 


The Gigabit Ethernet Tech. Family 


Support Link Distance 

1000BASE-LX 

1000BASE-SX 

1000BASE-T 

1000BASE-CX 

Balanced 

shielded cable 

25m 100m 220m 500m 550m 5km 

Machine 

room 

Horizontal 

wiring 

Building 

backbone 

Campus 

backbone 


Objectives 

Comply with specifications for GMII of 802.3z. 

Support the objectives of 802.3z of Nov. 13, 

1996. 

Provide line transmission which support full 

and half duplex operation. 

Support operation over 100 meters of 

Category 5 balanced cabling. 

4 Pairs 1Gb/s full duplex communication 

Achieve bit Error Rate better than to 10 -10 . 

Support Auto-Negotiation (Clause 28). 


Market Applications 

Server Network 

High-Performance Graphic-Based 

Applications 

Shared Gigabit Networks 

First-mile Applications (Ethernet as First Mile, 

EFM) 


Foundations 

100BASE-TX (CAT-5 UTP) 

– 3-level symbol stream at 125M Baud Rate 

– 100BASE-TX DSP Based PHY Is Available. 

100BASE-T2 (CAT-3 UTP) 

– 5-Level Coding 

– Simultaneous 2-Way data stream 

– Use of DSP (Echo and NEXT Cancellation) 

100BASE-T4 (CAT-3 UTP) 

– Transmit/Receive Multi-Level Coded Symbols 

over 4 Pairs 


Gigabit Ethernet Channel 

( CAT 5 UTP Cable ) 


The CAT 5 UTP Channel 

CAT 5 UTP is specified in ANSI/TIA/EIA-568-A:1995 

or equivalently in ISO/IEC 11801:1995 

125M Symbol/sec, 2bits/Symbol 

250Mb/s at each pair 

4 Pairs 1Gb/s full-duplex communication 

Transceivers 

Hybrid 

Hybrid 

Hybrid 

Hybrid 

Hybrid 

Hybrid 

Hybrid 

Hybrid 

Transceivers 


The Cable Challenge 


Channel Response – Insertion Loss 

Worst-Case Attenuation of 100m CAT 5 Cable 

Insertion_Loss(f) < 2.1f 0.529 +0.4/f (dB) 


Channel Response – Return Loss 

Return Loss Characteristic of 100m CAT 5 Cable 

Return_Loss(f) = 15 (dB), 1 ≤ f < 20 (MHz) 

Return_Loss(f) = 15-10*log 10 (f/20) (dB), 20 ≤ f < 100 (MHz) 


Channel Response – Crosstalk 

NEXT and FEXT Characteristics of 100m CAT 5 Cable 

 

 

NEXT_Loss > 27.1-16.8log 10 (f/100) dB 

ELFEXT_Loss(f) > 17-20log 10 (f/100) dB 


Channel Response - Total 


Channel Evaluation and Modeling 

1. Insertion loss 

•2. Return loss 

•3. NEXT 

•4. FEXT 

Attenuation (dB) 

0 

-10 

-20 

-30 

-40 

-50 

1 2 

3 

4 

-60 

0 10 20 30 40 50 60 70 80 90 100 

Frequency (MHz) 


What Is CAT 5E UTP Cable 

Enhanced Category 5 Unshielded Twisted Pair 

Cable. 

Specified in TIA/EIA-568-A-5 and TSB95. 

Why CAT 5E UTP 

– Better than CAT 5 in Echo and Crosstalk. 

– Some Parameters are undefined in the CAT 5 UTP. 

– Additional Parameters : FEXT, Return Loss, 

Propagation Delay,Delay Skew… 


How Much Better than CAT 5 UTP 


1000BASE-T Transceiver 


Review of Cable Challenge 


MLT-3 and PAM-5 Signal Levels 

5 Level Signaling Costs 6dB Lower than 100BASE-TX 


What are the Design Tasks 

Each pair a full duplex channel supporting effective data 

rate of 250Mbps in both directions simultaneously 

– Echo, Self-NEXT, and FEXT 

• Hybrid to cancel most of the Near-end ECHO 

• Adaptive cancellers to reduce remaining ECHO and Self-NEXT 

Signal-to-Noise Ratio (SNR) 6dB less than 100BASE-TX 

due to 5-level signaling 

– Provide 6dB coding gain in the form of 4-D Trellis code 

Channel Impairments 

– 20dB signal attenuation at 62MHz at 100 meters 

• Incorporate Decision-Feedback Channel Equalization 

– External Noise 

FCC impose limits on transmit levels 

– Limit transmit spectrum above 30MHz 

• Partial Response spectral shaping at the transmitter (3/4+1/4Z -1 ) 


Transmitter 


Transmitter (cont.) 


DSP Based Receiver Block Diagram 


Typical 100BASE-TX DSP Based Receiver 


What are New from 100BASE-TX 

to 1000BASE-T 

Pulse Pulse Pulse Pulse 

Shaping Shaping Shaping Shaping 

125MHz 

125MHz 

125MHz 

125MHz 

DAC 

DAC 

DAC 

DAC 

GMII 

PCS 

NEXT 

NEXT 

Cancellers 

Echo Echo Echo Echo 

Cancellers 

Hybrid 

DFE & TCM 

Decoder 

+ 

FFE FFE FFE 

125MHz 

ADC 

ADC 

ADC 

AFE AFE AFE AFE 

Timing Recovery 


Design Issues in Gigabit 

Receiver 


Major Receiver Design Works 

A/D conversion 

– 125 Mega samples per second Conversion 

Frequency Locking and Timing Recovery 

– Low Jitter Phase Locked Loop for clock recovery 

Echo/NEXT Canceller 

FEC – 4D 8-State Trellis Code 

Reduced-state Decision Feedback Equalizer 

– Design of critical timing path involving Trellis 

decoder and decision feedback equalizer 


Baseband DSP Component – 

Echo and NEXT Canceller 


Echo/NEXT Canceller 

Operating Frequency : 125MHz 

4 Echo Canceller each with 120 Taps 

12 NEXT Canceller each with 20 Taps 

‣ Low Cost and High Speed Long-Tap 

Adaptive Filter 


Echo and NEXT Canceller Structure 

x(n) 

FIR Filter 

y(n) 

Error 

Calculation 

r(n) 

e(n) 

Adaptive 

Theorem 

h k (n+1)=h k (n)+µe(n)x(n-k) 


Echo and NEXT Canceller Structure (cont.) 



Trellis Encoder 


MLT-3 and PAM-5 Signal Levels 

5 Level Signaling Costs 6dB Lower than 100BASE-TX 

‣ Add Forward Error Correction (FEC) 


4D TCM for Gigabit Ethernet 

Purpose : Match the robustness of 3 level 100BASE- 

TX signaling with 5 level 1000BASE-T signaling. 

Implement as 2-steps approach : 

– Convolutional Encoding to convert scrambled octet data into 

9-bit word 

– Mapping by set partitioning to get 6dB noise immunity gain. 


4D TCM for Gigabit Ethernet (cont.) 



Equalizer 


Detail of DFE Based Equalizer 


Gigabit Receiver With FEC (Delayed Decision- 

Feedback Sequence Estimation (DDFSE) ) 


Baseband Design Issues 

DDFSE : 

- Evaluate/derive DDFSE algorithms and 

architectures 

- Implementational issues of Viterbi decoder 

- Low-latency adaptive DFE design 

Echo canceller and NEXT canceller 

-Low-cost/high-speed long taps adaptive filter 


System Simulations 

Algorithm of Timing Recovery and Adaptive Filters 

Loop Bandwidth Partition 

Tap Length of Adaptive Filter 

Bit Number (Wordlegnth) of Datapath 

Integration of Subsystems 


Receiver Design Parameter Comparison 


Case Study – Design Point : 10dB 


Case Study(cont’d) – Broadcom & Bell Lab. 

125MBaud, 2bit/symbol 

Pulse Shaping 

.75+.26z -1 

D/A 

Analog 

FE 

Analog Digital 

3 Next 

Cancel. 

A/ FIF 

FFE + 

D O 

From other transmitters 

From other receivers 

DFE+TCM 

decoder 

GMII 

PCS 

3 Next Cancellers 

Echo 

Can. 

Hybrid 

UTP 

Hybrid 

125M 

125M 

Echo 

Cancel. 

PCS 

GMII 

DFSE Trellis 

Decoder 

Σ 

FFE 

A/D 

25M 

DPLL 

Timing 

Recove 

ry 

Soft Decs. From 

Other Receivers 

Timing 

Recovery 

D/ 

A 

Pulse 

shaping 

Parameters 

Broadcom 

A B C 

Bell 

Lab. 

A/D resolution 6 7 8 7 or 8 

D/A resolution 6 7 8 17L 

FFE Taps 8 8 8 10-20 

DFE Taps 14 14 14 8 

Next Taps 80 80 80 20 

Echo Taps 60 60 60 120 

SNR 18.8db 24.4db 27.7db n/a 

7bit linearity 

10Bit Conf. 


Challenges for Design Gigabit Ethernet 

Modeling of Practical UTP Channels 

Need 4 Parallel High-Speed A/Ds and D/As 

Need Robust Equalizers to Overcome Echo, 

Crosstalk, and Channel Distortion Problems 

Algorithm to Realize DFE + 4-D TCM Decoder 

Very High Hardware Complexity for SOC Design 


NTUEE Research Works 


High-performance Pipelined ADFE Design Based 

on the PPBS scheme 

Design a pipelined ADFE in order to increase the 

throughput rate to meet the speed requirement of GBE 

systems and future very-high-speed communication 

systems. 

Approaches 

– Predictive Parallel Branch Slicer (PPBS) Scheme 


Speed Limitation of the Conventional 

ADFE 

•The highest clock rate is limited by Decision Feedback 

Loop (DFL) 

e(n) 

x(n) 

FFE 

D 

D 

WUC 

FBE 

D 

WUD 

DFL 


Review of Pipelined ADFE (Look-Ahead 

ADFE) 

 

 

Assume the error in the slicer 

output is small, the ADFE can be 

consider as the IIR filter. 

Apply the look-ahead technique, 

we can obtain the pipelined 

ADFE coefficients. 

N ( z) 

Q( 

z) 

N ( z) 

P( 

z) 

= = 

D( 

z) 

Q( 

z) 

D( 

z) 

Q( 

z) 

N( 

z) 

= 

− D + 1) 

1− 

z R( 

( 1 

z 

k 

with R ( z ) = 

∑= i 0 

r i z 

) 

−i 


Relaxed-ADFE 

 

 

 

Constraint the first D 1 taps to zeros 

Inserting extra D 1 delay to pipeline the DFL 

It suffers from the output SNR degradation 

Combined channel and FFE response 

x(n) 

D 2 

FFE 

D 4 

WUC 

e(n) 

FBE 

D 

DFL 

D 3 

D 4 

D 1 

The first D 1 

post-cursor ISI 

seen by FBE 

WUD 

D 3 

D 2 


Pipelined ADFE Based on PPBS (PPBS- 

ADFE) 

 

In wirelined communication, the average behavior of channel 

impulse response can be roughly measured by some instrument 

or theoretical analysis. (IOL channel model) 


D 2 

PPBS-ADFE (cont.) 

We can fix the first D 1 coefficients of the FBE according to the 

channel model. 

Constraint the first D 1 =2 taps to [c 1 c 2 ]. 

x(n) 

FFE 

e(n) 

D 

Combined channel and FFE response 

(D 1 

=2) 

c 1 

D 2 

D 4 

WUC 

FBE 

DFL 

D 3 

D 4 

c 2 

WUD 

D 3 

D 2 


PPBS-ADFE (cont.) 

 

 

Apply the look-ahead 

Computation technique, 

the iteration bound of DFL 

can be shorten by D 1 

times. 

The extra D 1 delay 

elements can be retimed 

to appropriate position to 

pipeline the critical path. 

V T T e 0 

V T e T 1 

e(n) 

x(n) 

y(n) b(n) 

D D 

FFE 

D 2 

D 4 

WUF 

An example of D 1 =2 

PPBS 

V T e T 22 

V T e T 23 

V T T e 24 

d 0 

d 23 

d 23 

d 24 

e t, 0 

e t,1 

e t, 24 

e t,22 

e t, 23 

25-to-1 MUX 

FBE 

D 4 

D 3 

WUB 

D 3 + 3 


Performance Analysis of PPBS- 

ADFE(II) 

Here, we define the 

Inaccuracy Index, 

T 

( V −V 

) ( V −V 

) 

e p e p 

Γ= 

. 

T 

V V 

Simulation results are 

close agreement with 

the theoretical results. 

p 

p 

Γ = 0 ( The Conventional ADFE) 

Γ = 0.3( 

PIPEADFE2) 

Γ = 1( 

PIPEADFE1) 


Comparisons of Hardware Complexity 

•S=D 1 +1, is the speedup factor 

Relaxed-ADFE 

PPBS-ADFE 

Mult. in FFF 

Mult. in FBF 

Total Adder 

2( 

N f 

+ S −1) 

2( 

+ S −1) 

N f 

2N b 

2N 

b 

2N 

+ 2N 

+ 2S 

− 3 

2N 

+ 2N 

+ 2S 

− 3 

f b 

f b 

Slicer 

5 S-1 -to-1 MUX 

1 

0 

5 S-1 

2 


Integration of Equalization and Timing 

Recovery 

 

The architecture of joint ADFE and timing recovery 

Rx 

Equalization 

Slicer 

Receive 

Clk 

Mux 

Loop 

filter 

Estimate 

timing 

error 

CLK 

Generater 

(40 Phase) 


Simulation Results of PPBS-ADFE 

 

 

 

Under the IOL worst case environment (100BASE-T) 

Using the 7-bit A/D converter 

The output SNR in slicer is about 20.22dB (>18.4dB) 


Simulation Results of PPBS-ADFE 

 

 

 

Under the IOL worst case environment (1000BASE-T) 

Using 8-bit A/D converter 

The output SNR in slicer is about 24.6dB (>21.3dB) 


Performance in Different Cable 

Length 

 

The longer cable has the larger attenuation (lower SNR). 


CHIP Summary of PPBS-ADFE 

Using Avanti! 0.35µm standard cell library (WCOM) (critical path =4.69 ns) 

Cell Library 

Voltage 

Die Size 

Core Size 

Gate Count 

Power 

I/O Pad 

Avanti! 0.35μm 1P4M 

3.3V 

2.712mm ×2.712mm 

1.31mm ×1.31mm 

32,839 

957mW@ 250MHz 

40 


Conclusions 

 

Gigabit Ethernet will become the major trend for 

Ethernet applications within a short period. 

The GBE design has more demand on DSP than 

analog circuit designs. 

A typical SOC design example and challenge. 

Research work in NTUEE: A high-performance 

pipelined PPBS-ADFE for the future high-speed 

communications system is demonstrated. 


References 

 

 

 

 

 

 

 

IEEE Std802.3ab, 1999. Available from 

http://grouper.ieee.org/groups/802/3/search.html 

M. Hatamian, O.E. Agazzi, et al. "Design Considerations for Gigabit 

Ethernet 1000BASE-T Twisted Pair Transceivers", Proceedings of CICC, 

1998 

K. Azadet "Gigabit Ethernet over Unshielded Twisted Pair Cables", 

Proceedings of VLSI-TSA conference, Taipei, June 1999 

E. Haratsch "High-Speed VLSI Implementation of Reduced Complexity 

Sequence Estimation Algorithms with Application to Gigabit Ethernet 

1000BASE-T", Proceedings of VLSI-TSA conference, Taipei, June 1999 

J.Everitt, J. Parker, P. Hurst, D. Nack, K. Konda, C. Raad " A CMOS 

transceiver for 10-Mb/s and 100Mb/s Ethernet", IEEE JSSC, Vol.33, No. 12, 

Dec. 1998, pp.2169-2177 

http://www.agilent .com 

http://www.gigabit-ethernet.org 


References (cont’d) 

 

 

 

 

 

 

E. F. Haratsch, "High-speed VLSI implementation of reduced complexity 

sequence estimation algorithms with application to Gigabit Ethernet 

1000BASE-T," Proc. Int. Symp. VLSI-TSA, Taipei, pp. 171-174, Jun. 1999. 

E. F. Haratsch and K. Azadet, "A low complexity joint equalizer and 

decodeer for 1000BASE-T Gigabit Ethernet," Proc. IEEE CICC, Orlando, pp. 

465-468, May 2000. 

E. F. Haratsch, A. J. Blanksby and K. Azadet, "Reduce-state sequence 

estimation with tap-selectable decision-feedback," Proc. IEEE Int. Conf. 

Commun.(ICC), New Orleans, Jun. 2000. 

Alexandra Duel-Hallen and Chris Heegard, " Delayed decision-feedback 

sequence estimation“ Trans. IEEE Comm., Vol.37, No. 5, May 1989,pp.428- 

436. 

M. Vedat Eyuboglu and Shahid U. H. Qureshi, "Reduced-state sequence 

estimation for coded modulation on intersymbol interference 

channels“ IEEE JSAC, Vol. 7, No. 6, Auguest 1989 

Erich F Haratsch, Kamean Azadet, "A 1-Gb/s joint equalizer and trellis 

decoder for 1000BASE-T Gigabit Ethernet “ IEEE Journal of solid-state 

circuit, Vol. .36, No. 3 ,March 2001

Overview of Gigabit Ethernet Transceiver IC Design

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