Semiconductor Memory Testing - Laboratory for Reliable Computing

Semiconductor Memory
Testing
Cheng-Wen Wu 吳 誠 文
Lab for Reliable Computing (LARC)
Dept. Electrical Engineering
National Tsing Hua University

Syllabus (1/5)
• EE625300 Semiconductor Memory Testing
• Course Description
− This is an advanced course for VLSI Testing and Design for
Testability, with emphasis on semiconductor memory
testing. It is recommended that you take EE6250 (or
equivalent) first.
• Textbook
− L.-T. Wang, C.-W. Wu, and X. Wen, Design for Testability:
VLSI Test Principles and Architectures, Elsevier (Morgan
Kaufmann), San Francisco, 2006
• Reference
− Ad J. van de Goor, Testing Semiconductor Memories:
Theory and Practice, John Wiley & Sons, Chichester,
England, 1991
m01intro10.02 Cheng-Wen Wu, NTHU 2

Syllabus (2/5)
• Format
− Lectures, homework, and term project
• Course Outline
−
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Introduction and fundamentals of IC testing
RAM on-line testing
RAM functional fault models
RAM test algorithms
RAM fault-coverage analysis
Cocktail-March for testing word-oriented memories
Memory built-in self-test (BIST)
Memory built-in self-diagnosis (BISD)
Memory redundancy repair
Memory built-in self-repair (BISR)
Memory failure analysis
Testing flash memories
Flash memory BIST
Other advanced topics
m01intro10.02 Cheng-Wen Wu, NTHU 3

• Grading Policy
− Homework 30%
Syllabus (3/5)
− Midterm exams 40% (2x20%)
− Project 30%
• TAs
− MS Lee 李 旻 昇 mslee@larc.ee.nthu.edu.tw
− CY Chen 陳 靜 怡 cychen95@larc.ee.nthu.edu.tw
• URL
− http://larc.ee.nthu.edu.tw/~cww/n/625/6253/6253.html
− http://larc.ee.nthu.edu.tw/~mslee/
m01intro10.02 Cheng-Wen Wu, NTHU 4

Syllabus (4/5)
• Tentative Schedule
− 2/23: Introduction
− 3/2: Fundamentals of IC testing
− 3/9: RAM on-line testing (Prof. SK Lu)
− 3/16: RAM functional fault models
− 3/23: RAM test algorithms (Prof. JF Li)
− 3/30: RAM fault-coverage analysis
− 4/6: Cocktail-March for testing word-oriented
memories
− 4/13: Memory built-in self-test (BIST)
− 4/20: Midterm Exam I
− 4/27: Memory built-in self-diagnosis (BISD)
m01intro10.02 Cheng-Wen Wu, NTHU 5

Syllabus (5/5)
• Tentative Schedule
− 5/4: Memory redundancy repair
− 5/11: Memory built-in self-repair (BISR)
− 5/18: Memory failure analysis
− 5/25: Midterm Exam II
− 6/1: Testing flash memories
− 6/8: Flash memory BIST
− 6/15: Other advanced topics
− 6/18 (Friday): Project report due
m01intro10.02 Cheng-Wen Wu, NTHU 6

Outline
• Introduction & fundamentals of IC testing
• RAM on-line testing
• RAM functional fault models & test algorithms
• RAM fault-coverage analysis & test generation
• Testing word-oriented & multi-port memories
• Memory built-in self-test (BIST) & built-in self-diagnosis
(BISD)
• Memory redundancy analysis and built-in self-repair
(BISR)
• Memory failure analysis
• Testing non-volatile memories
m01intro10.02 Cheng-Wen Wu, NTHU 7

Chapter 1: Introduction and
Fundamentals of IC Testing
Cheng-Wen Wu 吳 誠 文
Lab for Reliable Computing
Dept. Electrical Engineering
National Tsing Hua University

• Scope of testing
Outline
• Defect level and fault coverage
• Fault models
− Classical faults
− Switch-level faults
− Timing faults
− Memory faults
• Test and testing
• Design for testability (DFT)
• Introduction to memory testing
m01intro10.02 Cheng-Wen Wu, NTHU 9

What Are Tests
Nuclear test, Nevada, 1953
[science.howstuffworks.com]
∗Olympic ticket test: Canada vs. Brazil
∗[www.cbc.ca]
∗Wafer test
∗[www.nikhef.nl]
∗Color vision test
∗[colorvisiontesting.co
m]
∗Compression strength
test
∗[esquel-epp.com.my]

Test
• Definition of test [Merriam-Webster]:
− A critical examination, observation, or
evaluation
− The procedure of submitting a statement to
such conditions or operations as will lead to its
proof or disproof or to its acceptance or
rejection
• All products need to be tested
• How do you test an advanced CPU
• How do you test a DDR3 DRAM
• Why do you test them

Typical IC Production Flow
Wafer
Probe Test
Packaging
Visual Inspection
Final Test
Marking
QA Sample Test
Shipping
m01intro10.02 Cheng-Wen Wu, NTHU 12

• Economics!
− Product quality
− Product reliability
Why Testing
Defect detected
during IC test
Defect detected
during system test
Defect detected
during field test
m01intro10.02 Cheng-Wen Wu, NTHU 13

Semiconductor Trends (ITRS 2005)
Matel 1 Helf Pitch
100
90
80
70
60
50
40
30
20
10
0
Shrinking Pitch Size
2005 2010 2015 2020
# of Wirin
18.5
18
17.5
17
16.5
16
15.5
15
14.5
Increasing Wiring Levels
2005 2010 2015 2020
Year of Production
Year of Production
Gbits/cm
50
45
40
35
30
25
20
15
10
5
0
Increasing Gate Density
2005 2010 2015 2020
Power Supply Voltage
1.2
1
0.8
0.6
0.4
0.2
0
Decreasing Supply Voltage
2005 2010 2015 2020
Year of Production
Year of Production
m01intro10.02 Cheng-Wen Wu, NTHU 14

Test Cost
90
80
70
60
50
40
30
20
10
0
0.5um 0.35um 0.25um 0.18um
Test cost
Package cost
Silicon cost
m01intro10.02 Cheng-Wen Wu, NTHU 15

DFT Usage Trend
m01intro10.02 Cheng-Wen Wu, NTHU 16

Scope of Testing
• Engineering Test
− Diagnostic Test
∗ Fault location
∗ Failure analysis
∗ Design and/or process debugging
• Manufacturing Test
− Characterization Test
∗ Performance characterization: parametric test
∗ Reliability characterization: bathtub curve (aging)
− Production Test
∗ Simple parametric test
∗ Functional test
∗ Reliability screening (burn-in)
m01intro10.02 Cheng-Wen Wu, NTHU 17

Fault
• Fault: a physical defect in a circuit/system
− Permanent fault: a fault that is continuous and stable, whose
nature do not change before, during, and after testing
∗ Affecting the functional behavior of the system permanently
∗ A.k.a. hard fault or solid fault
∗ Usually quite localized
∗ Can be modeled
− Temporary fault: a fault that is present only part of the time,
occurring at random moments and affecting the system for
finite, but unknown, intervals of time
∗ Transient fault: caused by environmental conditions
∗ No well-defined fault model
∗ Called soft error in RAM
∗ Often assumed no permanent damage was done
− Intermittent fault: caused by non-environmental conditions
∗ Often repeatable
∗ Can use permanent fault models and repeated test with stress
m01intro10.02 Cheng-Wen Wu, NTHU 18

Fault Model and Error
• Fault model: logical effect of a fault
− Structure faults
∗ Stuck-at faults: stuck-at-0 and stuck-at-1
∗ Bridging (short) fault
∗ Open (break) fault
∗ Transistor stuck-on and stuck-open faults
∗ Transition and delay faults
− Functional faults
∗ RAM coupling and pattern-sensitive faults
∗ PLA cross-point faults
• Error: manifestation of a fault that results in
an incorrect module output or system state
m01intro10.02 Cheng-Wen Wu, NTHU 19

Failure
• Failure: deviation of a system from its
specified behavior
− Fault → error → failure
• Failure mechanism: physical or chemical
process that causes devices to malfunction;
they manifest themselves on the circuit
level as failure modes
• Failure mode: the cause of rejection of
failed device (effect of failure mechanism),
such as open/short interconnections, or
degraded parameter values
m01intro10.02 Cheng-Wen Wu, NTHU 20

Testing and Fault Coverage
• Testing is the process of determining whether a
device functions correctly or not
− How much testing of an IC is enough
• Yield (Y) is the ratio of the number of good dies
per wafer to the number of dies per wafer
• Fault coverage (FC) is the measure of the ability
of a test set T to detect a given set of faults that
may occur on the DUT
− FC = (#detected faults)/(#possible faults)
m01intro10.02 Cheng-Wen Wu, NTHU 21

Defect Level and Fault Coverage
• Defect level (DL) is the fraction of bad parts
among the parts that pass all tests and are
shipped
− DL = 1 – Y**(1-FC)
• FC refers to the real defect coverage (probability
that T detects any possible fault---in F or not)
• DL is measured in terms of DPM (defects per
million), and typical values claimed are less than
200 DPM, or 0.02%
m01intro10.02 Cheng-Wen Wu, NTHU 22

Defect Level and Fault Coverage
Required FC for DL = 200 DPM.
Y (%)
10
50
90
95
99
FC(%)
99.99
99.97
99.8
99.6
98
m01intro10.02 Cheng-Wen Wu, NTHU 23

The Testing Problem
• Given a set of faults in the circuit under test
(CUT), how do we obtain a certain (small)
number of test patterns which guarantees a
certain (high) fault coverage
− What faults to test (fault modeling)
− How are test patterns obtained (test pattern
generation)
− How is test quality (fault coverage) measured
(fault simulation)
− How are test vectors applied and results evaluated
(ATE/BIST)
m01intro10.02 Cheng-Wen Wu, NTHU 24

Logic Fault Modeling: Stuck-at Fault
a
b
c c stuck-at 0; c s-a-0; c s/0, or c/0
a b c c(a/0) c(a/1) c(b/0) c(b/1) c(c/0) c(c/1)
0 0
0 1
1 0
1 1
0
0
0
1
0
0
0
0
0
1
0
1
• Single (line) stuck-at fault: line has a constant value (0/1)
• Multiple stuck fault: several single stuck-at faults occur at
the same time
− For a circuit with k lines, there are 2k single stuck faults, and 3 k -1
multiple stuck faults
0
0
0
0
0
0
1
1
0
0
0
0
1
1
1
1
m01intro10.02 Cheng-Wen Wu, NTHU 25

Test
• A test for a fault f in circuit C is an input
combination for which the output(s) of C is
different when f is present than when it is
not
− A.k.a. test pattern, test vector, or experiment
− A test x detects fault f iff C(x)⊕C f (x)=1
• A test set for a class of faults F is a set of
tests T such that for any fault f∈F, there
exists t∈T such that t detects f
m01intro10.02 Cheng-Wen Wu, NTHU 26

Fault Diagnosis
• Fault detection: tells only whether a circuit
is fault-free or not
• Fault identification (location; isolation):
provides the location and the type of the
detected fault and other related information
• Fault diagnosis: includes both fault
detection and fault identification
m01intro10.02 Cheng-Wen Wu, NTHU 27

Testing
• Testing is a process which includes test
pattern generation, test pattern application,
and output evaluation
− The quality of a test set depends on its fault
coverage (FC) as well as its size
− FC (typically 98-99% single stuck faults for
logic circuit) can be determined by fault
simulation
m01intro10.02 Cheng-Wen Wu, NTHU 28

Design for Testability (DFT)
• A fault is testable if there exists a well-specified
procedure to expose it, which can be
implemented with a reasonable cost using current
technologies
− A circuit is testable with respect to a fault set when
each and every fault in this set is testable
• The term DFT refers to a class of design
methodologies which put constraints on the
design process to make test generation and
diagnosis easier
• Testability = controllability + observability
m01intro10.02 Cheng-Wen Wu, NTHU 29

DFT Dilemma
• No single methodology solves all VLSI testing
problems
• No single DFT technique is effective for all kinds
of circuits
• No DFT approach is free
− Manpower and tool costs
− Area overhead and performance penalty
• Two classes of DFT techniques
− Ad hoc guidelines
− Structured (systematic) techniques
m01intro10.02 Cheng-Wen Wu, NTHU 30

MUX Scan
x
Combinational
Logic
C
T
SI
M D M D M D
SO
1. Switch to SR mode and check SR operation
2. Initialize SR---load the first pattern
3. Return to normal mode and apply test pattern
4. Switch to SR mode and shift out the final state while
setting the starting state for the next test. Go to 3
m01intro10.02 Cheng-Wen Wu, NTHU 31

x
LFSR
Circular BIST
Mux
SI
SO
Combinational
Logic
MISR
z
MISR
m01intro10.02 Cheng-Wen Wu, NTHU 32

Scan-Based PS-BIST with Test Points
L
F
S
R
• • •
PI
P
S
M
U
X
to cps
• • •
Combinational
Logic
• • •
• • •
• • •
• • •
S
C
from ops
• • •
PO
M
I
S
R
Source: K.-T. Tim Cheng, UCSB
m01intro10.02 Cheng-Wen Wu, NTHU 33

Why Investigating Memory Testing
• Memory testing is a more and more important issue
− RAMs are key components for electronic systems
∗ In Alpha 21264, cache RAMs represent 2/3 transistors and 1/3 area;
in StrongArm SA110, the embedded RAMs occupy 90% area [Bhavsar,
ITC-99]
∗ Memory cores will represent more than 90% of SOC area by 2010
[ITRS 2001]
− Memories represent about 30% of the semiconductor market
− Embedded memories are dominating the chip yield
• Memory testing is more and more difficult
− Growing density, capacity, and speed
− Emerging new architectures and technologies
− Embedded memories: access, diagnostics & repair, heterogeneity,
custom design, power & noise, scheduling, compression, etc.
• Cost drives the need for more efficient test methodologies
− IFA, fault modeling and simulation, test algorithm development and
evaluation, diagnostics, DFT, BIST, BIRA, BISR, etc.
m01intro10.02 Cheng-Wen Wu, NTHU 34

Embedded Memory Testing
• Embedded memory testing is increasingly difficult
− High bandwidth (speed and I/O data width)
− Heterogeneity and plurality
− Isolation (accessibility)
− AC test, diagnostics, and repair
• Test automation is required
− Failure analysis, fault simulation, ATG, and
diagnostics
− BIST/BIRA/BISR generation
m01intro10.02 Cheng-Wen Wu, NTHU 35

Typical RAM Production Flow
Wafer
Full Probe Test
Laser Repair
Packaging
Marking
Post-BI Test
Burn-In (BI)
Pre-BI Test
Final Test
Visual Inspection
QA Sample Test
Shipping
m01intro10.02 Cheng-Wen Wu, NTHU 36

Off-Line Testing of RAM
• Parametric Test: DC & AC
• Reliability Screening
− Long-cycle testing
− Burn-in: static & dynamic BI
• Functional Test
− Device characterization
∗ Failure analysis
− Fault modeling
∗ Simple but effective (accurate & realistic)
− Test algorithm generation
∗ Small number of test patterns (data backgrounds)
∗ High fault coverage
∗ Short test time
m01intro10.02 Cheng-Wen Wu, NTHU 37