2nd Annual c-Si PVMC Workshop Report

U.S. PVMC Report: 2 nd Annual c-Si PVMC Workshop - 2013 

U.S. PVMC Report 

2 nd Annual c-Si PVMC Workshop – 

San Francisco, CA 

H.P. Seigneur, K.O. Davis, A.C. Rudack, W.V. Schoenfeld 

July 10 th , 2013

U.S. PVMC Report: 2 nd Annual c-Si PVMC Workshop Summary - 2013 

Summary 

On July 10 th , 2013 the U.S. Photovoltaic Manufacturing Consortium (U.S. PVMC) held our 2 nd 

Annual c-Si Workshop in San Francisco, CA during the Intersolar NA conference. The 

general purpose of this workshop is identify critical industry challenges and needs, which 

is the first step in the process of establishing collaborative projects in c-Si programs at the 

PVMC and thus enabling the development new c-Si technologies. 

Our 2 nd Annual c-Si Workshop was organized into two sessions, a morning session focusing 

on current manufacturing challenges and an afternoon session focusing on barriers to 

mainstream manufacturing for emerging c-Si technologies. Both morning and afternoon 

sessions consisted of presentations on needs, challenges, and trends in the areas of 

feedstock, wafering, and metrology within they own respective focus. 

Because our annual c-Si PVMV Workshops are intended to stimulate and foster open 

discussion, we use a panel discussion with PV manufacturers during the morning session 

and an open discussion during the afternoon session to further expound on identified 

challenges and understand their associations with near and long-term needs in the 

industry.


Participants 

First Name Last Name Email Address Affiliation 

Brent Ames Brent_Ames@amat.com Applied Materials 

Stephen Gould stephen.gould@anu.edu.au Australian National University 

Marcie Black marcie@bandgap.com Bandgap Engineering 

Michael Jura mike@bandgap.com Bandgap Engineering 

Patrick Looney jlooney@bnl.gov Brookhaven National Laboratory 

KV Ravi kvravi510@gmail.com Consultant 

Doug Hall drdouglaswhall@gmail.com DOE 

Neelkanth Dhere dhere@fsec.ucf.edu Florida Solar Energy Center 

Andrew Gabor andrew@gaborpv.com Gabor Photovoltaics Consulting 

Simeon Baker-Finch simeon.baker-finch@hanwhasolar.us Hanwha Solar America 

Bidhan Chaudhuri bidhanpc@yahoo.com Hanwha Solar America 

Emmanuel Van 

evk@hanwhasolar.us 

Hanwha Solar America 

Kerschaver 

Abraham Michelen a.michelen@hvcc.edu HVCC 

Michael Woodhouse michael.woodhouse@nrel.gov NREL 

Anthony Broomer tbroomer@verizon.net Process Research 

Kris Davis Kris.Davis@uspvmc.org PVMC 

Andrew Rudack andy.rudack@uspvmc.org PVMC 

Winston Schoenfeld Winston.Schoenfeld@uspvmc.org PVMC 

Hubert Seigneur hubert.seigneur@uspvmc.org PVMC 

Ramesh Gopalan ramesh.gopalan@roshan-energy.com Roshan Energy 

dan holladay Dan.Holladay@sematech.org SEMATECH 

Stephan Raithel sraithel@semi.org SEMI 

Ron Sinton ron@sintoninstruments.com Sinton Instruments 

Stella Su ssu@solarbuyer.com SolarBuyer LLC 

Kristina Loge kloge@solarbuyer.com SolarBuyer LLC 

homi fatemi homi.fatemi@solexel.com Solexel 

Steve Hogan shogan@spirecorp.com Spire 

John Benner jpbenner@stanford.edu Stanford University 

Ethan Good ethan.good@sunedison.com SunEdison 

Atul Gupta agupta@suniva.com Suniva 

Greg Horner ghorner@tauscience.com Tau Science Corporation 

Sergei Ostapenko sergei.ostapenko@ultrasonictech.com Ultrasonic Technologies


Workshop Agenda 1 

8:00a – 8:50a Registration/Breakfast 

8:50a – 9:00a Opening Remarks – Winston Schoenfeld, c-Si U.S.PVMC 

Session 1: Current Needs and Challenges for PV Manufacturers 

9:00a – 9:30a SunEdison – Ethan Good 

9:30a – 10:00a Suniva – Atul Gupta 

10:00a – 10:30a GTM Research – Andrew Gabor 

10:30a – 10:45a Coffee Break/Networking 

10:45a – 11:15a SEMI – Stephan Raithel 

11:15a – 11:45a Solexel – Homi Fatemi 

11:45a – 12:15p Panel Discussion on PV Manufacturing Challenges 

12:15a – 1:15p Lunch/Networking 

Session 2: Emerging c-Si Technologies – Barriers to Mainstream 

Manufacturing 

1:15p – 1:40p Consultant – KV Ravi 

1:40p – 2:00p Florida Solar Energy Center – Kris Davis 

2:00p – 2:00p Bay Area PV Consortium – John Benner 

2:20p – 2:40p Applied Materials – Brent Ames 

2:40p – 2:50p Coffee Break/Networking 

2:50p – 3:10p Hanwha - Simeon Baker-Finch 

3:10p – 3:30p Australia National University – Stephen Gould 

3:30p – 3:50p Bandgap Engineering – Marcie Black 

3:50a – 4:10p National Renewable Energy Laboratory – Michael Woodhouse 

4:10p – 4:40p Open Discussion 

4:40p – 4:45p Wrap-up / Adjourn 

1To download the 2013 2 nd Annual c-Si PVMC Workshop materials, refer to the following link: 

http://www.uspvmc.org/event_archives.html


Summary of Challenges 

This section summarizes both near-term and long-term challenges. Although our initial c-Si 

programs focus on feedstock, wafering, and metrology, the summary of challenges includes 

challenges not directly associated to these production areas and are classified as others. Also, the 

summary tables were generated from the additional slides on challenges requested from each 

speaker. 

Near-Term Challenges (1-3 Years) 

Metrology Feedstock/Wafering Others 

Universal IV testing for solar cells 

Low-Cost, High-Purity, Flowable 

Feedstocks to Further Improve Minority 

Carrier Lifetime of Substrates 

Full wafer characterization 

Mitigating LID in pType Substrates and/or 

Migration to nType Substrates for 

Industrial Architectures 

100% EL/PL inspection of modules Low Thermal Budget Fabrication 

Sequences and/or Engineered Oxygen 

Defects 

Reflectivity measurements, Cell IV testing, Eliminate LID for p-type mono 

and Module IV Testing should simulate inlaminate 

conditions and field conditions 

Wafer Handling, Optical Confinement and 

Passivation at Thicknesses < 120 um 

Cosmetics/Quality specs 

Optimized matching of cells during 

stringing/assembly 

Interconnect ribbon reliability 

Cell IV testers that can contact fingers Inherently crack-resistant wafers/cells Cell-sorter binning algorithms. Take into 

account performance at nonstandard 

conditions 

A fast, accurate approach for 

characterizing surface recombination 

velocity. This becomes particularly 

important as wafer thickness is reduced 

A reliable method for differentiating bulk 

recombination from surface 

recombination 

Method for characterizing light trapping 

effectiveness for various approaches to 

light trapping 

Mechanical property characterization of 

thin wafers – fracture strength, time 

induced crack propagation, etc 

Improving methods of turning data into 

useful information 

Better methods of quantifying light 

trapping enhancements (not the same 

thing as reflectance) 

Decoupling surface and bulk 

recombination 

Correlating stress/strain to cracks 

Further reduction in process costs for 

poly-Si 

Epitaxial Wafers – Reactors (Scaling, 

capacity, and maintenance) 

Epitaxial Wafers – Reusable substrate 

(supply line issue and increase reuse) 

Epitaxial Wafers – Consumables use, 

energy use, cost, availability 

Scaling up of n-type wafer production 

Improving diamond wire saw technology 

to enable thinner and thinner wafers 

Recycling of kerf fines 

Creation and optimization of wafering 

baselines to drive cell efficiency and yield 

improvements 

Cell-to-module conversion w/o power loss 

Throughput increase (front-end & backend) 

Efficiency increase with existing lines / 

technologies 

Silver reduction / plating technologies 

Reliability of 50um thick epi-Si solar cells 

Lack of capital investment 

Cell and module reliability 

Creation and optimization of cell 

manufacturing baselines to drive cell 

efficiency and yield improvements 

Surface recombination metrology and 

mechanisms 

Making and handling of thin (


Long-Term Challenges (4+ Years) 

Integrated tool level SPC 

Metrology Feedstock/Wafering Others 

Defect characterization and root cause 

analysis 

Controlling Growth Front in Direct Wafer 

Formation Approaches 

Closed-Loop Waste Si Recycling 

Wafer Preparation, Handling, Optical 

Confinement and Passivation at 

Thicknesses < 80 um 

Improving Spectral Harvesting (Down 

Conversion, Hetero/Tandem Structures) 

to Push c-Si Beyond S.Q. Limits 

Warranty rating for each module 

Materials qualifications 

Rectangular wafers and updated 

tooling/process/handling equipment 

Accelerated reliability testing Wafer thickness reduction New performance metrics on specs sheets. 

Predict kWh/yr for a few different 

standardized locations and install 

conditions 

Quantifying recombination in novel 

wafer/cell formats 

Low cost methods of characterizing bulk 

and surface impurities/contaminants 

Predicting reliability/durability issues 

upstream by integrating metrology data 

with predictive models 

Measuring thin silicon quality 

Implementation of new sawing 

technologies 

Further reduction in process costs for 

poly-Si 

Adoption of lower cost and lower energy 

consumption synthesis routes for 

polysilicon 

Faster ways to validate new feedstock and 

wafering technologies to investors in 

terms of performance, reliability, etc. 

Glass-glass / frameless 

Silver replacement (printing vs. Plating) 

Automation & cell-to-module integration 

Cell and module process integration for 

thin kerfless wafers 

Light trapping, low reflection without 

consumption of Si 

Texturing of kerfless wafers 

Thin silicon – handling issues, specialized 

tools


Session 1: Panel Discussion 

The following section provides an overview of the panel discussion that covered four 

topical areas: (1) Thin wafers, (2) Metrology, (3) Mono-like, and (4) Concerns about c-Si PV. 

Before these topics were covered, the following question was asked: What is the best 

shape of a wafer/cell (pseudo square, square, rectangular) To get a square shape, 

225mm diameter is needed. Larger ingots in case of continuous Cz or n-type (Fz) comes at 

a cost. There are re-melt issues (cropping large amount of materials), growth issues 

(quality of material at the edges degrades), and performance issues (efficiency at the edges 

drops); all these resulting in diminishing return. Eventually 225+ mm diameter will happen 

because of new metallization schemes requiring a square shape. Ultimately, full half-square 

cells are desirable. 

1 – Thin wafers 

What are the biggest barriers for adoption of thin wafer technology It is mentioned 

that this question was similar to the question about the chicken and the egg, which came 

first The anticipated reduction in thicknesses of wafer is delayed each year. Is it the


manufacturers’ fault or the suppliers’ Everyone wants to go thinner but no one makes a 

move. Retooling may be required since current equipment specs is limited to 160um 

thicknesses minimum, although not tested for smaller thickness. Retooling is difficult since 

everyone is cash strapped. No manufacturer will guarantee that they would buy the 

equipment if developed. They are also technical challenges at the microcracks level 

(soldering), light trapping, and handling. Right now, before thinking about going thinner, 

the best situation might be to make the transition to PERC, and then think about going 

thinner. 

2 – Metrology 

When choosing to implement a metrology technique, what drives your decision 

making process the most Are we talking about “preventive” metrology or “process 

control/in-line” metrology The first type looks good for the first year in terms or ROI but 

then becomes irrelevant. The later one is important and needed constantly specially as cell 

architectures and fabrication processes become more sophisticated/complicated. Basically 

the drivers are need, ROI, performance improvement at reduced cost, integrated process 

control. 

3 – Mono-like Silicon 

Do you believe that the industry will adopt mono-like technology in the future Based 

on current and projected interest from ITRPV roadmap, it is not the technology of choice. 

Manufacturers in Asia rather stick to the high-performance multi-crystalline Si. In terms of 

market share, the point was made that the projections for high-performance multi-Si still 

showing 50% of the market in 2023, which does not make sense since the targeted 

efficiencies and cell architectures would require most-likely mono. It was also noted that 

mono-like seems to be the natural progression for multi-Si and there was nowhere else 

multi could go. Last, SunEdison has abandoned all multi/mono-like effort. 

4 – Concerns about c-Si PV 

What is the single thing about c-Si PV that keeps you up at night 

1. Bad press from misinformed “expert” that is being repeated and amplified 

2. Cost-cutting practices will eventually bite us back as products fail in the field 

possibly resulting in a Solyndra 2.0 scenario. 

3. How to innovate in cash strapped market 

4. Much of the silicon material is wasted


Session 2: Open Discussion 

The open discussion during the afternoon session centered on cost modeling and what was 

required to stay competitive. The approaches were discussed: 

1. NREL’s document, “A Wafer-Based Monocrystalline Silicon Photovoltaics Roadmap” 

2. Learning curve for module prices as a function of cumulative module shipment 

The model estimates an average “long-term” sustainable total module manufacturing cost 

to be around $0.64/Wp in the best case scenario for a U.S. based manufacturer (IBC cell at 

22.4% that is 80um thick). On the other hand, the average sales prices (ASPs) according to 

the later model are estimated to transition from $0.70/Wp in 2012 to $0.55/Wp in 2015. 

This seems to indicate that the anticipated decline in cost will continue to render PV 

manufacturing difficult to sustain.


Summary and Conclusions 

In conclusion, the 2 nd Annual c-Si PVMC Workshop was very successful. With 32 participants 

coming from a variety of different industrial and academic backgrounds, many thought 

provoking and stimulating topics were covered in the area of c-Si PV manufacturing. Speakers 

and attendees were all able to share their perspective on current and future challenges for c-Si 

PV manufacturing and provide input on potential barriers for emerging c-Si technologies. Many 

different points of view were shared, as both technical and market-related topics were debated 

by the workshop participants. The PVMC will use this valuable input when moving forward with 

the c-Si Programs.

2nd Annual c-Si PVMC Workshop Report

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