Programmable Logic Design Quick Start Handbook

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PROGRAMMABLE LOGIC DESIGN: QUICK START HANDBOOK • CHAPTER 2 SYSTEM RESOURCES DSP Central These web pages detail the XtremeDSP solutions that deliver the performance and flexibility needed to quickly build complex, high-performance DSP systems. Driven by the broadband revolution and explosive growth in wireless products, the demand for digital signal processing featuring extreme performance and great flexibility is growing faster than what conventional DSP can deliver. The rapid convergence of different technology segments – 3G and 4G wireless communication systems, high-bandwidth networking, real-time video broadcasting, and high-performance computing systems – is producing what analysts call ”The beginning of a new information technology era.” Xilinx, the recognized leader in programmable logic solutions, is well established in these technology segments and uniquely positioned to address this new DSP paradigm now. The XtremeDSP solution can give you computing capabilities approaching 1 Tera MAC/s – more than 100 times faster than conventional DSP solutions. Using our comprehensive line of industry-leading FPGAs, easy-to-use tools, and optimized algorithms, along with the most comprehensive technical support, services, and third-party programs in the industry, you’ll have the confidence to tackle even the most challenging applications using the Xilinx XtremeDSP tool. DSP Central provides information that will enable you to achieve the maximum benefit from Xilinx DSP solutions. This section provides details and design information in the following areas: Algorithms/Cores In this comprehensive listing of intellectual property, you can search for algorithms by type: • DSP Cores • Communication and Networking • Video/Image Processing • IP Updates. XILINX ONLINE (IRL) You can access and upgrade hardware from your desktop anywhere in the world with the Xilinx IRL capability. The mission of the Xilinx Online program is to enable, identify, and promote any Xilinx programmable system that is connected to a network that can Xilinx • 82
XILINX SOLUTIONS be fixed, upgraded, or otherwise modified after the system has been deployed in the field. The design technology for creating Xilinx Online applications is called Internet Reconfigurable <strong>Logic</strong>, or IRL. IRL design technology comprises robust PLD technology, your network connectivity, and software design tools. Put these individual pieces together and network-based hardware upgradeability becomes a reality. You can access details through the “Systems Resources” main web page or visit www.xilinx.com/irl. CONFIGURATION SOLUTIONS Located under the “Products and Services” section of the Xilinx website, this section provides easy-to-use, pre-engineered solutions to configure all Xilinx FPGAs and CPLDs. All aspects of configuration are explained, whether from a PROM for FPGAs or via ISP for CPLDs. The section also includes third-party Boundary Scan tools, embedded software solutions, ISP cables, ATE and programmer support, and configuration storage devices. PROCESSOR CENTRAL This section provides information that will enable you to reap maximum benefits from Xilinx FPGA processing solutions. It offers the freedom to design a custom solution with a choice of hard processors (as many as four embedded PowerPC processors in Virtex-II Pro devices) or soft processors (with the MicroBlaze soft processor core and Pico- Blaze microprocessor core in Virtex-II, Virtex-E, Spartan-II, and Spartan-IIE FPGAs). Processor Central also includes more than 40 soft processor peripherals and the necessary embedded software tools to easily complete your design. The Processor Central section has the following detailed web pages: The Embedded Development Kit (EDK) EDK is an all-encompassing solution for designing embedded programmable systems using the IBM PowerPC hard processor core and the Xilinx Micro- Blaze soft processor core in Xilinx FPGAs. PowerPC Embedded Processor Solution Embedding IBM's PowerPC processor core into the Virtex-II Pro FPGA provides the ultimate platform FPGA solution. The UltraController Solution Xilinx offers a powerful, easy-to-use Virtex-II Pro FPGA PowerPC-based microcontroller solution ideal for embedded hardware and software applications. Xilinx • 83
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Programmable Logic Design Quick Sta
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ABSTRACT Whether you design with di
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NAVIGATING THIS BOOK C HAPTER 5: IM
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TABLE OF CONTENTS Virtex FPGAs.....
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TABLE OF CONTENTS MicroBlaze and Pi
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Chapter 7: Design Reference Bank TA
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C HAPTER 1 Introduction The History
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INTRODUCTION Other architectures fo
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INTRODUCTION vides an instant hardw
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INTRODUCTION FIGURE 1-4: FPGA ARCHI
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INTRODUCTION By using Xilinx CoolRu
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INTRODUCTION FIGURE 1-8: DESIGN SPE
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INTRODUCTION For the HDL specificat
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INTRODUCTION Even if you decide to
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INTRODUCTION original I/O pin place
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INTRODUCTION FIGURE 1-11: DEVICE IM
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C HAPTER 2 Xilinx Solutions Introdu
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XILINX SOLUTIONS The Platform FPGA
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. XILINX SOLUTIONS FIGURE 2-2: PLAT
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XILINX SOLUTIONS FIGURE 2-4: SPARTA
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XILINX SOLUTIONS • Full- and half
Page 43 and 44: TABLE 2-3: SPARTAN-3 FEATURES AND B
Page 45 and 46: XILINX SOLUTIONS FIGURE 2-6: SPARTA
Page 47 and 48: XILINX SOLUTIONS FIGURE 2-8: SPARTA
Page 49 and 50: XILINX SOLUTIONS FIGURE 2-10: SPART
Page 51 and 52: Delay-Locked Loop XILINX SOLUTIONS
Page 53 and 54: XILINX SOLUTIONS FIGURE 2-15: SPART
Page 55 and 56: XILINX SOLUTIONS Low Power - Is you
Page 57 and 58: XILINX SOLUTIONS XC9500XL family is
Page 59 and 60: XILINX SOLUTIONS TABLE 2-5: XC9500X
Page 61 and 62: XILINX SOLUTIONS caded chain of pur
Page 63 and 64: XILINX SOLUTIONS FIGURE 2-22: COOLR
Page 65 and 66: I/O Cell XILINX SOLUTIONS The outpu
Page 67 and 68: TABLE 2-6: VFM (Variable Function M
Page 69 and 70: XILINX SOLUTIONS Figure 2-27 also d
Page 71 and 72: XILINX SOLUTIONS At the high level,
Page 73 and 74: XILINX SOLUTIONS FIGURE 2-30: COOLR
Page 75 and 76: XILINX SOLUTIONS The larger parts (
Page 77 and 78: XILINX SOLUTIONS Note that a synchr
Page 79 and 80: XILINX SOLUTIONS These security bit
Page 81 and 82: XILINX SOLUTIONS COOLRUNNER REFEREN
Page 83 and 84: . XILINX SOLUTIONS FIGURE 2-42: LOG
Page 85 and 86: XILINX SOLUTIONS To address the nee
Page 87 and 88: XILINX SOLUTIONS This rich mixture
Page 89 and 90: Dynamic Verification XILINX SOLUTIO
Page 91 and 92: XILINX SOLUTIONS Xilinx IP Cores Th
Page 93: XILINX SOLUTIONS • Test and Measu
Page 97 and 98: XILINX SOLUTIONS TABLE 2-10: XILINX
Page 99 and 100: XILINX SOLUTIONS CONNECTIVITY CENTR
Page 101 and 102: XILINX SOLUTIONS design • Broad a
Page 103 and 104: Xilinx Student Edition Frequently A
Page 105 and 106: C HAPTER 3 WebPACK ISE Design Softw
Page 107 and 108: WEBPACK ISE DESIGN SOFTWARE 4. Gene
Page 109 and 110: WEBPACK ISE DESIGN SOFTWARE WEBPACK
Page 111 and 112: Summary PROJECTS WEBPACK ISE DESIGN
Page 113 and 114: C HAPTER 4 WebPACK ISE Design Entry
Page 115 and 116: WEBPACK ISE DESIGN ENTRY FIGURE 4-2
Page 117 and 118: WEBPACK ISE DESIGN ENTRY Notice tha
Page 119 and 120: WEBPACK ISE DESIGN ENTRY As you hav
Page 121 and 122: WEBPACK ISE DESIGN ENTRY The area s
Page 123 and 124: WEBPACK ISE DESIGN ENTRY Click OK t
Page 125 and 126: WEBPACK ISE DESIGN ENTRY Maximize t
Page 127 and 128: WEBPACK ISE DESIGN ENTRY Open the S
Page 129 and 130: WEBPACK ISE DESIGN ENTRY Set RD to
Page 131 and 132: WEBPACK ISE DESIGN ENTRY In the edi
Page 133 and 134: Click on the Generate HDL button on
Page 135 and 136: WEBPACK ISE DESIGN ENTRY Click on t
Page 137 and 138: WEBPACK ISE DESIGN ENTRY Connect th
Page 139 and 140: You are now ready to go to the impl
Page 141 and 142: WEBPACK ISE DESIGN ENTRY Move the c
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C HAPTER 5 Implementing CPLDs Intro
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IMPLEMENTING CPLDS The design shoul
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IMPLEMENTING CPLDS Notice that the
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DoubLe-click in the Period window o
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IMPLEMENTING CPLDS In the Clock to
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IMPLEMENTING CPLDS Click on the “
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IMPLEMENTING CPLDS To open the CPLD
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IMPLEMENTING CPLDS MXE will open, b
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C HAPTER 6 Implementing FPGAs Intro
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IMPLEMENTING FPGAS Double-click on
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IMPLEMENTING FPGAS The FSM encoding
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IMPLEMENTING FPGAS The Constraints
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IMPLEMENTING FPGAS Highlight the th
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IMPLEMENTING FPGAS Save and close t
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IMPLEMENTING FPGAS Programming Righ
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C HAPTER 7 Design Reference Bank In
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DESIGN REFERENCE BANK A high-powere
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DESIGN REFERENCE BANK USING A MICRO
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DESIGN REFERENCE BANK port ( clk :
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DESIGN REFERENCE BANK vated, it wil
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DESIGN REFERENCE BANK Figure 7-7 sh
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DESIGN REFERENCE BANK Full-function
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DESIGN REFERENCE BANK TABLE 7-1: DO
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DESIGN REFERENCE BANK TABLE 7-1: DO
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ACRONYMS ABEL ADC AIM ANSI ASIC ASS
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ACRONYMS LVDS Low Voltage Different
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PROGRAMMABLE LOGIC DESIGN -- QUICK
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