Programmable Logic Design Quick Start Handbook

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PROGRAMMABLE LOGIC DESIGN: QUICK START HANDBOOK • CHAPTER 2 I/O Blocks I/O blocks are primarily transceivers. However, each I/O is either automatically compliant with standard voltage ranges or can be programmed to become compliant. In addition to voltage levels, each input can selectively arrive through Schmitt-trigger inputs. This adds a small time delay, but substantially reduces noise on that input pin. Hysteresis also allows easy generation of external clock circuits. The Schmitt-trigger path is best illustrated in Figure 2-31. Outputs can be directly driven, tri-stated, or open-drain configured. A choice of slow or fast slew rate output signal is also available. FIGURE 2-31: COOLRUNNER-II I/O BLOCK Xilinx • 62 Output Banking CPLDs are widely used as voltage interface translators; thus, the output pins are grouped in large banks. The smallest parts are not banked, so all signals will have the same output swing for 32- and 64-macrocell parts. The medium parts (128 and 256 macrocell) support two output banks. With two, the outputs will switch to one of two selected output voltage levels, unless both banks are set to the same voltage.
XILINX SOLUTIONS The larger parts (384 and 512 macrocell) support four output banks, split evenly. They can support groupings of one, two, three, or four separate output voltage levels. This kind of flexibility permits easy interfacing to 3.3V, 2.5V, 1.8V, and 1.5V in a single part. DataGATE Low power is the hallmark of CMOS technology. Other CPLD families use a sense amplifier approach to create p-terms, which always has a residual current component. This residual current can be several hundred milliamps, making these CPLDs unusable in portable systems. CoolRunner-II CPLDs use standard CMOS methods to create the CPLD architecture and deliver the corresponding low current consumption, without any special tricks. However, sometimes you might want to reduce the system current even more by selectively disabling unused circuitry. The patented DataGATE technology permits a straightforward approach to additional power reduction. Each I/O pin has a series switch that can block the arrival of unused freerunning signals that may increase power consumption. Disabling these switches enables you to complete your design and choose which sections will participate in the DataGATE function. FIGURE 2-32: DATAGATE FUNCTION IN COOLRUNNER-II CPLDS The DataGATE logic function drives an assertion rail threaded through medium- and high-density CoolRunner-II CPLD parts. Xilinx • 63
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Programmable Logic Design Quick Sta
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ABSTRACT Whether you design with di
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NAVIGATING THIS BOOK C HAPTER 5: IM
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TABLE OF CONTENTS Virtex FPGAs.....
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TABLE OF CONTENTS MicroBlaze and Pi
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Chapter 7: Design Reference Bank TA
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C HAPTER 1 Introduction The History
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INTRODUCTION Other architectures fo
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INTRODUCTION vides an instant hardw
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INTRODUCTION FIGURE 1-4: FPGA ARCHI
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INTRODUCTION By using Xilinx CoolRu
Page 23 and 24: INTRODUCTION FIGURE 1-8: DESIGN SPE
Page 25 and 26: INTRODUCTION For the HDL specificat
Page 27 and 28: INTRODUCTION Even if you decide to
Page 29 and 30: INTRODUCTION original I/O pin place
Page 31 and 32: INTRODUCTION FIGURE 1-11: DEVICE IM
Page 33 and 34: C HAPTER 2 Xilinx Solutions Introdu
Page 35 and 36: XILINX SOLUTIONS The Platform FPGA
Page 37 and 38: . XILINX SOLUTIONS FIGURE 2-2: PLAT
Page 39 and 40: XILINX SOLUTIONS FIGURE 2-4: SPARTA
Page 41 and 42: XILINX SOLUTIONS • Full- and half
Page 43 and 44: TABLE 2-3: SPARTAN-3 FEATURES AND B
Page 49 and 50: XILINX SOLUTIONS FIGURE 2-10: SPART
Page 51 and 52: Delay-Locked Loop XILINX SOLUTIONS
Page 53 and 54: XILINX SOLUTIONS FIGURE 2-15: SPART
Page 55 and 56: XILINX SOLUTIONS Low Power - Is you
Page 57 and 58: XILINX SOLUTIONS XC9500XL family is
Page 59 and 60: XILINX SOLUTIONS TABLE 2-5: XC9500X
Page 61 and 62: XILINX SOLUTIONS caded chain of pur
Page 63 and 64: XILINX SOLUTIONS FIGURE 2-22: COOLR
Page 65 and 66: I/O Cell XILINX SOLUTIONS The outpu
Page 67 and 68: TABLE 2-6: VFM (Variable Function M
Page 69 and 70: XILINX SOLUTIONS Figure 2-27 also d
Page 71 and 72: XILINX SOLUTIONS At the high level,
Page 73: XILINX SOLUTIONS FIGURE 2-30: COOLR
Page 77 and 78: XILINX SOLUTIONS Note that a synchr
Page 79 and 80: XILINX SOLUTIONS These security bit
Page 81 and 82: XILINX SOLUTIONS COOLRUNNER REFEREN
Page 83 and 84: . XILINX SOLUTIONS FIGURE 2-42: LOG
Page 85 and 86: XILINX SOLUTIONS To address the nee
Page 87 and 88: XILINX SOLUTIONS This rich mixture
Page 89 and 90: Dynamic Verification XILINX SOLUTIO
Page 91 and 92: XILINX SOLUTIONS Xilinx IP Cores Th
Page 93 and 94: XILINX SOLUTIONS • Test and Measu
Page 95 and 96: XILINX SOLUTIONS be fixed, upgraded
Page 97 and 98: XILINX SOLUTIONS TABLE 2-10: XILINX
Page 99 and 100: XILINX SOLUTIONS CONNECTIVITY CENTR
Page 101 and 102: XILINX SOLUTIONS design • Broad a
Page 103 and 104: Xilinx Student Edition Frequently A
Page 105 and 106: C HAPTER 3 WebPACK ISE Design Softw
Page 107 and 108: WEBPACK ISE DESIGN SOFTWARE 4. Gene
Page 109 and 110: WEBPACK ISE DESIGN SOFTWARE WEBPACK
Page 111 and 112: Summary PROJECTS WEBPACK ISE DESIGN
Page 113 and 114: C HAPTER 4 WebPACK ISE Design Entry
Page 115 and 116: WEBPACK ISE DESIGN ENTRY FIGURE 4-2
Page 117 and 118: WEBPACK ISE DESIGN ENTRY Notice tha
Page 119 and 120: WEBPACK ISE DESIGN ENTRY As you hav
Page 121 and 122: WEBPACK ISE DESIGN ENTRY The area s
Page 123 and 124: WEBPACK ISE DESIGN ENTRY Click OK t
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WEBPACK ISE DESIGN ENTRY Maximize t
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WEBPACK ISE DESIGN ENTRY Open the S
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WEBPACK ISE DESIGN ENTRY Set RD to
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WEBPACK ISE DESIGN ENTRY In the edi
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Click on the Generate HDL button on
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WEBPACK ISE DESIGN ENTRY Click on t
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WEBPACK ISE DESIGN ENTRY Connect th
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You are now ready to go to the impl
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WEBPACK ISE DESIGN ENTRY Move the c
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Your completed schematic should loo
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C HAPTER 5 Implementing CPLDs Intro
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IMPLEMENTING CPLDS The design shoul
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IMPLEMENTING CPLDS Notice that the
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DoubLe-click in the Period window o
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IMPLEMENTING CPLDS In the Clock to
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IMPLEMENTING CPLDS Click on the “
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IMPLEMENTING CPLDS To open the CPLD
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IMPLEMENTING CPLDS MXE will open, b
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C HAPTER 6 Implementing FPGAs Intro
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IMPLEMENTING FPGAS Double-click on
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IMPLEMENTING FPGAS The FSM encoding
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IMPLEMENTING FPGAS The Constraints
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IMPLEMENTING FPGAS Highlight the th
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IMPLEMENTING FPGAS Save and close t
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IMPLEMENTING FPGAS Programming Righ
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C HAPTER 7 Design Reference Bank In
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DESIGN REFERENCE BANK A high-powere
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DESIGN REFERENCE BANK USING A MICRO
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DESIGN REFERENCE BANK port ( clk :
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DESIGN REFERENCE BANK vated, it wil
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DESIGN REFERENCE BANK Figure 7-7 sh
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DESIGN REFERENCE BANK Full-function
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DESIGN REFERENCE BANK TABLE 7-1: DO
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DESIGN REFERENCE BANK TABLE 7-1: DO
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ACRONYMS ABEL ADC AIM ANSI ASIC ASS
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ACRONYMS LVDS Low Voltage Different
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PROGRAMMABLE LOGIC DESIGN -- QUICK
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