Programmable Logic Design Quick Start Handbook
Programmable Logic Design Quick Start Handbook
Programmable Logic Design Quick Start Handbook
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XILINX SOLUTIONS<br />
The larger parts (384 and 512 macrocell) support four output banks, split<br />
evenly. They can support groupings of one, two, three, or four separate output<br />
voltage levels. This kind of flexibility permits easy interfacing to 3.3V, 2.5V, 1.8V,<br />
and 1.5V in a single part.<br />
DataGATE<br />
Low power is the hallmark of CMOS technology. Other CPLD families use<br />
a sense amplifier approach to create p-terms, which always has a residual current<br />
component.<br />
This residual current can be several hundred milliamps, making these<br />
CPLDs unusable in portable systems.<br />
CoolRunner-II CPLDs use standard CMOS methods to create the CPLD<br />
architecture and deliver the corresponding low current consumption, without<br />
any special tricks.<br />
However, sometimes you might want to reduce the system current even<br />
more by selectively disabling unused circuitry. The patented DataGATE technology<br />
permits a straightforward approach to additional power reduction.<br />
Each I/O pin has a series switch that can block the arrival of unused freerunning<br />
signals that may increase power consumption. Disabling these<br />
switches enables you to complete your design and choose which sections will<br />
participate in the DataGATE function.<br />
FIGURE 2-32:<br />
DATAGATE FUNCTION IN COOLRUNNER-II CPLDS<br />
The DataGATE logic function drives an assertion rail threaded through<br />
medium- and high-density CoolRunner-II CPLD parts.<br />
Xilinx • 63