Programmable Logic Design Quick Start Handbook
Programmable Logic Design Quick Start Handbook
Programmable Logic Design Quick Start Handbook
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TABLE OF CONTENTS<br />
Virtex FPGAs........................................................................................................ 24<br />
Spartan FPGAs..................................................................................................... 25<br />
Spartan-3 FPGAs........................................................................................ 25<br />
Shift register SRL16 blocks ............................................................ 27<br />
As much as 520 Kb distributed SelectRAM memory ............ 27<br />
As much as 1.87 Mb Embedded block RAM .............................. 27<br />
Memory Interfaces .......................................................................... 27<br />
Multipliers ....................................................................................... 28<br />
XCITE Digitally Controlled Impedance Technology – ............ 28<br />
Spartan-3 XCITE DCI Technology Highlights ........................... 28<br />
Full- and half-impedance input buffers ...................................... 29<br />
Spartan-3 Features and Benefits ................................................. 29<br />
Spartan-IIE FPGAs .................................................................................... 31<br />
Spartan-IIE Architectural Features ......................................................... 32<br />
<strong>Logic</strong> Cells ....................................................................................... 35<br />
Block RAM ....................................................................................... 37<br />
Delay-Locked Loop ........................................................................ 38<br />
Configuration .................................................................................. 39<br />
Xilinx CPLDs ........................................................................................................ 41<br />
Product Features: ............................................................................ 41<br />
Selection Considerations: .............................................................. 41<br />
XC9500 ISP CPLD Overview ................................................................... 42<br />
XC9500 5V Family .......................................................................... 42<br />
Flexible Pin-Locking Architecture ............................................... 42<br />
Full IEEE 1149.1 JTAG Development and Debugging Support 42<br />
XC9500 Product Overview Table ................................................. 43<br />
XC9500XL 3.3V Family ............................................................................. 43<br />
Family Highlights ........................................................................... 44<br />
Performance ..................................................................................... 44<br />
Powerful Architecture .................................................................... 44<br />
Highest Reliability .......................................................................... 44<br />
Advanced Technology ................................................................... 44<br />
Outperforms All Other 3.3V CPLDs ............................................ 45<br />
XC9500XV 2.5V CPLD Family ................................................................. 45<br />
High Performance Through Advanced Technology ................. 45<br />
The System <strong>Design</strong>er’s CPLD ....................................................... 45<br />
CoolRunner Low-Power CPLDs ............................................................. 47<br />
XPLA3 Architecture ....................................................................... 48<br />
<strong>Logic</strong> Block Architecture ............................................................... 49<br />
FoldBack NANDs ........................................................................... 50<br />
Macrocell Architecture ................................................................... 51<br />
I/O Cell ............................................................................................ 52<br />
Simple Timing Model .................................................................... 52<br />
Slew Rate Control ........................................................................... 53<br />
XPLA3 Software Tools ................................................................... 53<br />
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