Programmable Logic Design Quick Start Handbook

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PROGRAMMABLE LOGIC DESIGN: QUICK START HANDBOOK • Table of Contents Navigating This Book Table of Contents Chapter 1: Introduction The History of Programmable Logic .................................................................. 1 Complex Programmable Logic Devices (CPLDs)............................................. 4 Why Use a CPLD ....................................................................................... 4 Field Programmable Gate Arrays (FPGAs) ....................................................... 6 Design Integration....................................................................................... 8 The Basic Design Process ..................................................................................... 9 HDL File Change Example ................................................................................ 13 Before (16 x 16 multiplier):....................................................................... 13 After (32 x 32 multiplier): ......................................................................... 13 Intellectual Property (IP) Cores......................................................................... 14 Design Verification.............................................................................................. 14 Functional Simulation .................................................................... 16 Device Implementation ................................................................. 16 Fitting ............................................................................................... 16 Place and Route .............................................................................. 17 Downloading or Programming .................................................... 18 System Debug ................................................................................. 19 Chapter 2: Xilinx Solutions Introduction.......................................................................................................... 21 Xilinx Devices....................................................................................................... 22 Platform FPGAs................................................................................................... 22 Virtex FPGAs ............................................................................................. 22 Virtex-II Pro FPGAs .................................................................................. 23 The Power of Xtreme Processing ................................................. 23 XtremeDSP – ................................................................................... 23 The Ultimate Connectivity Platform ........................................... 24 The Power of Integration................................................................ 24 Enabling a New Development Paradigm ................................... 24 Industry-Leading Tools ................................................................. 24 Xilinx • vi
TABLE OF CONTENTS Virtex FPGAs........................................................................................................ 24 Spartan FPGAs..................................................................................................... 25 Spartan-3 FPGAs........................................................................................ 25 Shift register SRL16 blocks ............................................................ 27 As much as 520 Kb distributed SelectRAM memory ............ 27 As much as 1.87 Mb Embedded block RAM .............................. 27 Memory Interfaces .......................................................................... 27 Multipliers ....................................................................................... 28 XCITE Digitally Controlled Impedance Technology – ............ 28 Spartan-3 XCITE DCI Technology Highlights ........................... 28 Full- and half-impedance input buffers ...................................... 29 Spartan-3 Features and Benefits ................................................. 29 Spartan-IIE FPGAs .................................................................................... 31 Spartan-IIE Architectural Features ......................................................... 32 Logic Cells ....................................................................................... 35 Block RAM ....................................................................................... 37 Delay-Locked Loop ........................................................................ 38 Configuration .................................................................................. 39 Xilinx CPLDs ........................................................................................................ 41 Product Features: ............................................................................ 41 Selection Considerations: .............................................................. 41 XC9500 ISP CPLD Overview ................................................................... 42 XC9500 5V Family .......................................................................... 42 Flexible Pin-Locking Architecture ............................................... 42 Full IEEE 1149.1 JTAG Development and Debugging Support 42 XC9500 Product Overview Table ................................................. 43 XC9500XL 3.3V Family ............................................................................. 43 Family Highlights ........................................................................... 44 Performance ..................................................................................... 44 Powerful Architecture .................................................................... 44 Highest Reliability .......................................................................... 44 Advanced Technology ................................................................... 44 Outperforms All Other 3.3V CPLDs ............................................ 45 XC9500XV 2.5V CPLD Family ................................................................. 45 High Performance Through Advanced Technology ................. 45 The System Designer’s CPLD ....................................................... 45 CoolRunner Low-Power CPLDs ............................................................. 47 XPLA3 Architecture ....................................................................... 48 Logic Block Architecture ............................................................... 49 FoldBack NANDs ........................................................................... 50 Macrocell Architecture ................................................................... 51 I/O Cell ............................................................................................ 52 Simple Timing Model .................................................................... 52 Slew Rate Control ........................................................................... 53 XPLA3 Software Tools ................................................................... 53 Xilinx • vii
Page 1 and 2: Programmable Logic Design Quick Sta
Page 3 and 4: ABSTRACT Whether you design with di
Page 5: NAVIGATING THIS BOOK C HAPTER 5: IM
Page 9 and 10: TABLE OF CONTENTS MicroBlaze and Pi
Page 11 and 12: Chapter 7: Design Reference Bank TA
Page 13 and 14: C HAPTER 1 Introduction The History
Page 15 and 16: INTRODUCTION Other architectures fo
Page 17 and 18: INTRODUCTION vides an instant hardw
Page 19 and 20: INTRODUCTION FIGURE 1-4: FPGA ARCHI
Page 21 and 22: INTRODUCTION By using Xilinx CoolRu
Page 23 and 24: INTRODUCTION FIGURE 1-8: DESIGN SPE
Page 25 and 26: INTRODUCTION For the HDL specificat
Page 27 and 28: INTRODUCTION Even if you decide to
Page 29 and 30: INTRODUCTION original I/O pin place
Page 31 and 32: INTRODUCTION FIGURE 1-11: DEVICE IM
Page 33 and 34: C HAPTER 2 Xilinx Solutions Introdu
Page 35 and 36: XILINX SOLUTIONS The Platform FPGA
Page 37 and 38: . XILINX SOLUTIONS FIGURE 2-2: PLAT
Page 39 and 40: XILINX SOLUTIONS FIGURE 2-4: SPARTA
Page 41 and 42: XILINX SOLUTIONS • Full- and half
Page 43 and 44: TABLE 2-3: SPARTAN-3 FEATURES AND B
Page 49 and 50: XILINX SOLUTIONS FIGURE 2-10: SPART
Page 51 and 52: Delay-Locked Loop XILINX SOLUTIONS
Page 53 and 54: XILINX SOLUTIONS FIGURE 2-15: SPART
Page 55 and 56: XILINX SOLUTIONS Low Power - Is you
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XILINX SOLUTIONS XC9500XL family is
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XILINX SOLUTIONS TABLE 2-5: XC9500X
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XILINX SOLUTIONS caded chain of pur
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XILINX SOLUTIONS FIGURE 2-22: COOLR
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I/O Cell XILINX SOLUTIONS The outpu
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TABLE 2-6: VFM (Variable Function M
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XILINX SOLUTIONS Figure 2-27 also d
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XILINX SOLUTIONS At the high level,
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XILINX SOLUTIONS FIGURE 2-30: COOLR
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XILINX SOLUTIONS The larger parts (
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XILINX SOLUTIONS Note that a synchr
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XILINX SOLUTIONS These security bit
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XILINX SOLUTIONS COOLRUNNER REFEREN
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. XILINX SOLUTIONS FIGURE 2-42: LOG
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XILINX SOLUTIONS To address the nee
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XILINX SOLUTIONS This rich mixture
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Dynamic Verification XILINX SOLUTIO
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XILINX SOLUTIONS Xilinx IP Cores Th
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XILINX SOLUTIONS • Test and Measu
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XILINX SOLUTIONS be fixed, upgraded
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XILINX SOLUTIONS TABLE 2-10: XILINX
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XILINX SOLUTIONS CONNECTIVITY CENTR
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XILINX SOLUTIONS design • Broad a
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Xilinx Student Edition Frequently A
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C HAPTER 3 WebPACK ISE Design Softw
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WEBPACK ISE DESIGN SOFTWARE 4. Gene
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WEBPACK ISE DESIGN SOFTWARE WEBPACK
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Summary PROJECTS WEBPACK ISE DESIGN
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C HAPTER 4 WebPACK ISE Design Entry
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WEBPACK ISE DESIGN ENTRY FIGURE 4-2
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WEBPACK ISE DESIGN ENTRY Notice tha
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WEBPACK ISE DESIGN ENTRY As you hav
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WEBPACK ISE DESIGN ENTRY The area s
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WEBPACK ISE DESIGN ENTRY Click OK t
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WEBPACK ISE DESIGN ENTRY Maximize t
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WEBPACK ISE DESIGN ENTRY Open the S
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WEBPACK ISE DESIGN ENTRY Set RD to
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WEBPACK ISE DESIGN ENTRY In the edi
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Click on the Generate HDL button on
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WEBPACK ISE DESIGN ENTRY Click on t
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WEBPACK ISE DESIGN ENTRY Connect th
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You are now ready to go to the impl
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WEBPACK ISE DESIGN ENTRY Move the c
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Your completed schematic should loo
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C HAPTER 5 Implementing CPLDs Intro
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IMPLEMENTING CPLDS The design shoul
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IMPLEMENTING CPLDS Notice that the
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DoubLe-click in the Period window o
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IMPLEMENTING CPLDS In the Clock to
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IMPLEMENTING CPLDS Click on the “
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IMPLEMENTING CPLDS To open the CPLD
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IMPLEMENTING CPLDS MXE will open, b
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C HAPTER 6 Implementing FPGAs Intro
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IMPLEMENTING FPGAS Double-click on
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IMPLEMENTING FPGAS The FSM encoding
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IMPLEMENTING FPGAS The Constraints
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IMPLEMENTING FPGAS Highlight the th
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IMPLEMENTING FPGAS Save and close t
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IMPLEMENTING FPGAS Programming Righ
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C HAPTER 7 Design Reference Bank In
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DESIGN REFERENCE BANK A high-powere
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DESIGN REFERENCE BANK USING A MICRO
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DESIGN REFERENCE BANK port ( clk :
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DESIGN REFERENCE BANK vated, it wil
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DESIGN REFERENCE BANK Figure 7-7 sh
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DESIGN REFERENCE BANK Full-function
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DESIGN REFERENCE BANK TABLE 7-1: DO
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DESIGN REFERENCE BANK TABLE 7-1: DO
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ACRONYMS ABEL ADC AIM ANSI ASIC ASS
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ACRONYMS LVDS Low Voltage Different
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PROGRAMMABLE LOGIC DESIGN -- QUICK
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