Programmable Logic Design Quick Start Handbook
Programmable Logic Design Quick Start Handbook
Programmable Logic Design Quick Start Handbook
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XILINX SOLUTIONS<br />
Figure 2-27 also details the distribution of advanced features across the<br />
CoolRunner-II CPLD family. The family has uniform basic features, with<br />
advanced features included in densities where they are most useful. For example,<br />
it is unlikely that you would need four I/O banks on 32- and 64-macrocell<br />
parts, but very likely for 384- and 512-macrocell parts.<br />
The I/O banks are groupings of I/O pins using any one of a subset of compatible<br />
voltage standards that share the same V CCIO level. The clock division<br />
capability is less efficient on small parts, but more useful and likely to be used<br />
on larger ones. DataGATE technology, an ability to block and latch inputs to<br />
save power, is valuable in larger parts, but brings marginal benefit to small<br />
parts.<br />
FIGURE 2-27:<br />
COOLRUNNER-II FAMILY OVERVIEW<br />
CoolRunner-II Architecture Description<br />
The CoolRunner-II CPLD is a highly uniform family of fast, low-power<br />
devices. The underlying architecture is a traditional CPLD architecture, combining<br />
macrocells into function blocks interconnected with a global routing matrix,<br />
the Xilinx Advanced Interconnect Matrix (AIM).<br />
The function blocks use a PLA configuration that allows all product terms<br />
to be routed and shared among any of the macrocells of the function block.<br />
Xilinx • 57