Programmable Logic Design Quick Start Handbook

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PROGRAMMABLE LOGIC DESIGN: QUICK START HANDBOOK • CHAPTER 2 Xilinx CPLDs Currently, Xilinx offers CPLD products in two categories: XC9500 and CoolRunner devices. To choose a CPLD that’s right for you, review the product features below to identify the product family that fits your application. You should also review the selection considerations to choose the device that best meets your design criteria. Product Features: XC9500 Device – The XC9500 ISP CPLD families take complex programmable logic devices to new heights of performance, features, and flexibility. These families deliver industry-leading speeds while providing the flexibility of enhanced customer-proven pin-locking architecture, along with extensive IEEE Std.1149.1 JTAG Boundary Scan support. This CPLD family is ideal for high-speed, low-cost designs. CoolRunner Device – The CoolRunner CPLD families offer extreme low power, making them the leaders in an all-new market segment: portable electronics. With standby current in the low micro amps and minimal operational power consumption, these parts are ideal for any application is that is especially power sensitive, such as battery-powered or portable applications. The CoolRunner-II CPLD extends usage as it offers system-level features such as LVTTL and SSTL, clocking modes, and input hysteresis. Selection Considerations: To decide which device best meets your design criteria, take a minute to jot down your design specs (using the list below as a criteria reference). Next, go to a specific product family page to get more detailed information about the device you need. Density – Each part gives an equivalent “gate count,” or estimate of the logic density of the part. Number of Registers – Count up the number of registers you need for your counters, state machines, registers, and latches. The number of macrocells in the device must be at least this large. Number of I/O Pins – How many inputs and outputs does your design need Speed Requirements – What is the fastest combinatorial path in your design This will determine the Tpd (in nanoseconds) of the device. What is the fastest sequential circuit in your design This will tell you what fMax you need. Package – What electromechanical constraints are you under Do you need the smallest ball grid array package possible, or can you use a more ordinary QFP Or are you prototyping and need to use a socketed device, such as a PLCC package Xilinx • 42
XILINX SOLUTIONS Low Power – Is your end product battery- or solar-powered Does your design require the lowest power devices possible Do you have heat dissipation concerns System-Level Functions – Does your board have multi-voltage devices Do you need to level shift between these devices Do you need to square up clock edges Do you need to interface to memories and microprocessors XC9500 ISP CPLD OVERVIEW The high-performance, low-cost XC9500 families of Xilinx CPLDs are targeted for leading-edge systems that require rapid design development, longer system life, and robust field upgrade capability. The XC9500 families range in density from 36 to 288 macrocells and are available in 2.5-volt (XC9500XV), 3.3-volt (XC9500XL) and 5-volt (XC9500) versions. These devices support ISP, which allows manufacturers to perform unlimited design iterations during the prototyping phase, extensive system in-board debugging, program and test during manufacturing, and field upgrades. Based on advanced process technologies, the XC9500 families provide fast, guaranteed timing; superior pin locking; and a full JTAG-compliant interface. All XC9500 devices have excellent quality and reliability characteristics with a 10,000 program/erase cycle endurance rating and 20-year data retention. XC9500 5V Family The XC9500 ISP CPLD family features six devices ranging from 36 to 288 macrocells, with a wide variety of package combinations that both minimize board space and maintain package footprints as designs grow or shrink. The I/O pins allow direct interfacing to both 3- and 5-volt systems, while the latest in compact, easy-to-use CSP and BGA packaging gives you access to as many as 192 signals. Flexible Pin-Locking Architecture XC9500 devices, in conjunction with our fitter software, give you the maximum in routeability and flexibility while maintaining high performance. The architecture is feature-rich, including individual product term (p-term) output enables, three global clocks, and more p-terms per output than any other CPLD. The proven ability of the architecture to adapt to design changes while maintaining pin assignments has been demonstrated in countless real-world customer designs since the introduction of the XC9500 family. Full IEEE 1149.1 JTAG Development and Debugging Support The JTAG capability of the XC9500 family is the most comprehensive of any CPLD on the market. It features the standard support including BYPASS, SAM- PLE/PRELOAD, and EXTEST. Xilinx • 43
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Programmable Logic Design Quick Sta
Page 3 and 4: ABSTRACT Whether you design with di
Page 5 and 6: NAVIGATING THIS BOOK C HAPTER 5: IM
Page 7 and 8: TABLE OF CONTENTS Virtex FPGAs.....
Page 9 and 10: TABLE OF CONTENTS MicroBlaze and Pi
Page 11 and 12: Chapter 7: Design Reference Bank TA
Page 13 and 14: C HAPTER 1 Introduction The History
Page 15 and 16: INTRODUCTION Other architectures fo
Page 17 and 18: INTRODUCTION vides an instant hardw
Page 19 and 20: INTRODUCTION FIGURE 1-4: FPGA ARCHI
Page 21 and 22: INTRODUCTION By using Xilinx CoolRu
Page 23 and 24: INTRODUCTION FIGURE 1-8: DESIGN SPE
Page 25 and 26: INTRODUCTION For the HDL specificat
Page 27 and 28: INTRODUCTION Even if you decide to
Page 29 and 30: INTRODUCTION original I/O pin place
Page 31 and 32: INTRODUCTION FIGURE 1-11: DEVICE IM
Page 33 and 34: C HAPTER 2 Xilinx Solutions Introdu
Page 35 and 36: XILINX SOLUTIONS The Platform FPGA
Page 37 and 38: . XILINX SOLUTIONS FIGURE 2-2: PLAT
Page 39 and 40: XILINX SOLUTIONS FIGURE 2-4: SPARTA
Page 41 and 42: XILINX SOLUTIONS • Full- and half
Page 43 and 44: TABLE 2-3: SPARTAN-3 FEATURES AND B
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Page 51 and 52: Delay-Locked Loop XILINX SOLUTIONS
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Page 59 and 60: XILINX SOLUTIONS TABLE 2-5: XC9500X
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Page 81 and 82: XILINX SOLUTIONS COOLRUNNER REFEREN
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Page 87 and 88: XILINX SOLUTIONS This rich mixture
Page 89 and 90: Dynamic Verification XILINX SOLUTIO
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Page 95 and 96: XILINX SOLUTIONS be fixed, upgraded
Page 97 and 98: XILINX SOLUTIONS TABLE 2-10: XILINX
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Page 103 and 104: Xilinx Student Edition Frequently A
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C HAPTER 3 WebPACK ISE Design Softw
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WEBPACK ISE DESIGN SOFTWARE 4. Gene
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WEBPACK ISE DESIGN SOFTWARE WEBPACK
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Summary PROJECTS WEBPACK ISE DESIGN
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C HAPTER 4 WebPACK ISE Design Entry
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WEBPACK ISE DESIGN ENTRY FIGURE 4-2
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WEBPACK ISE DESIGN ENTRY Notice tha
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WEBPACK ISE DESIGN ENTRY As you hav
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WEBPACK ISE DESIGN ENTRY The area s
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WEBPACK ISE DESIGN ENTRY Click OK t
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WEBPACK ISE DESIGN ENTRY Maximize t
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WEBPACK ISE DESIGN ENTRY Open the S
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WEBPACK ISE DESIGN ENTRY Set RD to
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WEBPACK ISE DESIGN ENTRY In the edi
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Click on the Generate HDL button on
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WEBPACK ISE DESIGN ENTRY Click on t
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WEBPACK ISE DESIGN ENTRY Connect th
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You are now ready to go to the impl
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WEBPACK ISE DESIGN ENTRY Move the c
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Your completed schematic should loo
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C HAPTER 5 Implementing CPLDs Intro
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IMPLEMENTING CPLDS The design shoul
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IMPLEMENTING CPLDS Notice that the
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DoubLe-click in the Period window o
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IMPLEMENTING CPLDS In the Clock to
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IMPLEMENTING CPLDS Click on the “
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IMPLEMENTING CPLDS To open the CPLD
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IMPLEMENTING CPLDS MXE will open, b
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C HAPTER 6 Implementing FPGAs Intro
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IMPLEMENTING FPGAS Double-click on
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IMPLEMENTING FPGAS The FSM encoding
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IMPLEMENTING FPGAS The Constraints
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IMPLEMENTING FPGAS Highlight the th
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IMPLEMENTING FPGAS Save and close t
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IMPLEMENTING FPGAS Programming Righ
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C HAPTER 7 Design Reference Bank In
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DESIGN REFERENCE BANK A high-powere
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DESIGN REFERENCE BANK USING A MICRO
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DESIGN REFERENCE BANK port ( clk :
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DESIGN REFERENCE BANK vated, it wil
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DESIGN REFERENCE BANK Figure 7-7 sh
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DESIGN REFERENCE BANK Full-function
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DESIGN REFERENCE BANK TABLE 7-1: DO
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DESIGN REFERENCE BANK TABLE 7-1: DO
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ACRONYMS ABEL ADC AIM ANSI ASIC ASS
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ACRONYMS LVDS Low Voltage Different
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PROGRAMMABLE LOGIC DESIGN -- QUICK
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