Programmable Logic Design Quick Start Handbook

XILINX SOLUTIONS
FIGURE 2-6:
SPARTAN-IIE ARCHITECTURE
SPARTAN-IIE ARCHITECTURAL FEATURES
Spartan-IIE devices leverage the basic feature set of the Virtex-E architecture
to offer outstanding value. The basic CLB structure contains distributed
RAM and performs basic logic functions.
Four DLLs are used for clock management and can perform clock de-skew,
clock multiplication, and clock division. Clock de-skew can be done on an external
(board level) or internal (chip level) basis.
The block memory blocks are 4 Kb each and can be configured from 1 to 16
bits wide. Each of the two independent ports can be configured independently
for width.
The SelectIO feature allows many different I/O standards to be implemented
in the areas of chip-to-chip, chip-to-memory, and chip-to-backplane
interfaces.
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