Programmable Logic Design Quick Start Handbook

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PROGRAMMABLE LOGIC DESIGN: QUICK START HANDBOOK • CHAPTER 2 Multipliers • Enable simple arithmetic and math as well as advanced DSP functions, enabling you to derive more than 330 billion MACs/s of DSP performance • As many as 104 18 x 18 multipliers support 18-bit signed or 17-bit unsigned multiplication, which you can cascade to support wider bits • Constant coefficient multipliers: On-chip memories and logic cells work hand-in-hand to build compact multipliers with a constant operand • <strong>Logic</strong> Cell multipliers: Implement user-preferred algorithms such as Baugh-Wooley, Booth, Wallace tree, and others DCMs deliver sophisticated digital clock management that’s impervious to system jitter, temperature, voltage variations, and other problems typically found with PLLs integrated into FPGAs. • Flexible frequency generation from 25 MHz to 325 MHz • 100 ps jitter • Integer multiplication and division parameters • Quadrature and precision phase shift control • 0, 90, 180, 270 degrees • Fine grain control (1/256 clock period) for clock data synchronization • Precise 50/50 duty cycle generation • Temperature compensation XCITE Digitally Controlled Impedance Technology – A Xilinx Innovation I/O termination is required to maintain signal integrity. With hundreds of I/Os and advanced package technologies, external termination resistors are no longer viable. I/O termination dynamically eliminates drive strength variation due to process, temperature, and voltage fluctuations. Spartan-3 XCITE DCI Technology Highlights • Series and parallel termination for single-ended and differential standards • Maximum flexibility with support of series and parallel termination on all I/O banks • Input, output, bidirectional, and differential I/O support • Wide series impedance range • Popular standard support, including LVDS, LVDSEXT, LVCMOS, LVTTL, SSTL, HSTL, GTL, and GTLP Xilinx • 28
XILINX SOLUTIONS • Full- and half-impedance input buffers TABLE 2-1: XCITE DCI TECHNOLOGY ADVANTAGES Advantage Second Generation Technology Lower Costs Absolute I/O Flexibility Maximum I/O Bandwidth Immunity to Temperature and Voltage Changes Eliminates Stub Reflection Increases System Reliability Details Proven in the field and used extensively by customers Fewer resistors, fewer PCB traces, and smaller board area, result in lower PCB costs. Any termination on any I/O bank. Non- XCITE technology alternatives deliver limited functionality Less ringing and reflections maximize I/O bandwidth Temperature and voltage variations lead to significant impedance mismatches. XCITE technology dynamically adjusts on-chip impedance to such variations reducing and improving reliability Improves discrete termination techniques by eliminating the distance between the package pin and resistor. Fewer components on board, deliver higher reliability TABLE 2-2: Device Spartan-3 Features and Benefits SPARTAN-3 FPGA FAMILY OVERVIEW XC 3S50 XC 3S200 XC 3S400 XC 3S1000 XC 3S1500 SC 3S2000 XC 3S4000 XC 3S5000 System Gates 50K 200K 400K 1000K 1500K 2000K 4000K 5000K <strong>Logic</strong> Cells 1,728 4,320 8,064 17,280 29,952 46,080 62,208 74,880 18x18 Multipliers 4 12 16 24 32 40 96 104 Block RAM Bits 72K 216K 288K 432K 576K 720K 1,728K 1,872K Distributed RAM Bits 12K 30K 56K 120K 208K 320K 432K 520K Xilinx • 29
Page 1 and 2: Programmable Logic Design Quick Sta
Page 3 and 4: ABSTRACT Whether you design with di
Page 5 and 6: NAVIGATING THIS BOOK C HAPTER 5: IM
Page 7 and 8: TABLE OF CONTENTS Virtex FPGAs.....
Page 9 and 10: TABLE OF CONTENTS MicroBlaze and Pi
Page 11 and 12: Chapter 7: Design Reference Bank TA
Page 13 and 14: C HAPTER 1 Introduction The History
Page 15 and 16: INTRODUCTION Other architectures fo
Page 17 and 18: INTRODUCTION vides an instant hardw
Page 19 and 20: INTRODUCTION FIGURE 1-4: FPGA ARCHI
Page 21 and 22: INTRODUCTION By using Xilinx CoolRu
Page 23 and 24: INTRODUCTION FIGURE 1-8: DESIGN SPE
Page 25 and 26: INTRODUCTION For the HDL specificat
Page 27 and 28: INTRODUCTION Even if you decide to
Page 29 and 30: INTRODUCTION original I/O pin place
Page 31 and 32: INTRODUCTION FIGURE 1-11: DEVICE IM
Page 33 and 34: C HAPTER 2 Xilinx Solutions Introdu
Page 35 and 36: XILINX SOLUTIONS The Platform FPGA
Page 37 and 38: . XILINX SOLUTIONS FIGURE 2-2: PLAT
Page 39: XILINX SOLUTIONS FIGURE 2-4: SPARTA
Page 43 and 44: TABLE 2-3: SPARTAN-3 FEATURES AND B
Page 45 and 46: XILINX SOLUTIONS FIGURE 2-6: SPARTA
Page 47 and 48: XILINX SOLUTIONS FIGURE 2-8: SPARTA
Page 49 and 50: XILINX SOLUTIONS FIGURE 2-10: SPART
Page 51 and 52: Delay-Locked Loop XILINX SOLUTIONS
Page 53 and 54: XILINX SOLUTIONS FIGURE 2-15: SPART
Page 55 and 56: XILINX SOLUTIONS Low Power - Is you
Page 57 and 58: XILINX SOLUTIONS XC9500XL family is
Page 59 and 60: XILINX SOLUTIONS TABLE 2-5: XC9500X
Page 61 and 62: XILINX SOLUTIONS caded chain of pur
Page 63 and 64: XILINX SOLUTIONS FIGURE 2-22: COOLR
Page 65 and 66: I/O Cell XILINX SOLUTIONS The outpu
Page 67 and 68: TABLE 2-6: VFM (Variable Function M
Page 69 and 70: XILINX SOLUTIONS Figure 2-27 also d
Page 71 and 72: XILINX SOLUTIONS At the high level,
Page 73 and 74: XILINX SOLUTIONS FIGURE 2-30: COOLR
Page 75 and 76: XILINX SOLUTIONS The larger parts (
Page 77 and 78: XILINX SOLUTIONS Note that a synchr
Page 79 and 80: XILINX SOLUTIONS These security bit
Page 81 and 82: XILINX SOLUTIONS COOLRUNNER REFEREN
Page 83 and 84: . XILINX SOLUTIONS FIGURE 2-42: LOG
Page 85 and 86: XILINX SOLUTIONS To address the nee
Page 87 and 88: XILINX SOLUTIONS This rich mixture
Page 89 and 90: Dynamic Verification XILINX SOLUTIO
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XILINX SOLUTIONS Xilinx IP Cores Th
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XILINX SOLUTIONS • Test and Measu
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XILINX SOLUTIONS be fixed, upgraded
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XILINX SOLUTIONS TABLE 2-10: XILINX
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XILINX SOLUTIONS CONNECTIVITY CENTR
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XILINX SOLUTIONS design • Broad a
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Xilinx Student Edition Frequently A
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C HAPTER 3 WebPACK ISE Design Softw
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WEBPACK ISE DESIGN SOFTWARE 4. Gene
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WEBPACK ISE DESIGN SOFTWARE WEBPACK
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Summary PROJECTS WEBPACK ISE DESIGN
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C HAPTER 4 WebPACK ISE Design Entry
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WEBPACK ISE DESIGN ENTRY FIGURE 4-2
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WEBPACK ISE DESIGN ENTRY Notice tha
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WEBPACK ISE DESIGN ENTRY As you hav
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WEBPACK ISE DESIGN ENTRY The area s
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WEBPACK ISE DESIGN ENTRY Click OK t
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WEBPACK ISE DESIGN ENTRY Maximize t
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WEBPACK ISE DESIGN ENTRY Open the S
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WEBPACK ISE DESIGN ENTRY Set RD to
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WEBPACK ISE DESIGN ENTRY In the edi
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Click on the Generate HDL button on
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WEBPACK ISE DESIGN ENTRY Click on t
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WEBPACK ISE DESIGN ENTRY Connect th
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You are now ready to go to the impl
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WEBPACK ISE DESIGN ENTRY Move the c
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Your completed schematic should loo
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C HAPTER 5 Implementing CPLDs Intro
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IMPLEMENTING CPLDS The design shoul
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IMPLEMENTING CPLDS Notice that the
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DoubLe-click in the Period window o
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IMPLEMENTING CPLDS In the Clock to
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IMPLEMENTING CPLDS Click on the “
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IMPLEMENTING CPLDS To open the CPLD
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IMPLEMENTING CPLDS MXE will open, b
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C HAPTER 6 Implementing FPGAs Intro
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IMPLEMENTING FPGAS Double-click on
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IMPLEMENTING FPGAS The FSM encoding
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IMPLEMENTING FPGAS The Constraints
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IMPLEMENTING FPGAS Highlight the th
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IMPLEMENTING FPGAS Save and close t
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IMPLEMENTING FPGAS Programming Righ
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C HAPTER 7 Design Reference Bank In
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DESIGN REFERENCE BANK A high-powere
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DESIGN REFERENCE BANK USING A MICRO
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DESIGN REFERENCE BANK port ( clk :
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DESIGN REFERENCE BANK vated, it wil
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DESIGN REFERENCE BANK Figure 7-7 sh
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DESIGN REFERENCE BANK Full-function
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DESIGN REFERENCE BANK TABLE 7-1: DO
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DESIGN REFERENCE BANK TABLE 7-1: DO
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ACRONYMS ABEL ADC AIM ANSI ASIC ASS
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ACRONYMS LVDS Low Voltage Different
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PROGRAMMABLE LOGIC DESIGN -- QUICK
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