Programmable Logic Design Quick Start Handbook

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PROGRAMMABLE LOGIC DESIGN: QUICK START HANDBOOK • CHAPTER 2 The Ultimate Connectivity Platform The first programmable device to combine embedded processors along with 3.125 Gbps transceivers, the Virtex-II Pro series of FPGAs addresses all existing connectivity requirements as well as the emerging high-speed interface standards. Xilinx RocketIO transceivers offer a complete serial interface solution, supporting 10 Gigabit Ethernet with XAUI, 3GIO, and SerialATA, among others. Our SelectIO-Ultra technology supports 840 Mbps LVDS and high-speed single-ended standards such as XSBI and SFI-4. The Power of Integration In a single off-the-shelf programmable device, you can take advantage of microprocessors, the highest density of on-chip memory, multi-gigabit serial transceivers, digital clock managers, on-chip termination, and more. The result is a dramatic simplification of board layout, a reduced bill of materials, and unbeatable time to market. Enabling a New Development Paradigm For the first time, you can partition and repartition your systems between hardware and software at any time during the development cycle – even after the product has shipped. This means you can optimize the overall system, guaranteeing your performance target in the most cost-efficient manner. You can also debug hardware and software simultaneously at speed. Industry-Leading Tools Optimized for the PowerPC, Wind River Systems's industry-proven embedded tools are the premier support for real-time microprocessor and logic designs. Driving the Virtex-II Pro FPGA is the Xilinx lightning-fast ISE software, the most comprehensive, easy-to-use development system available. Virtex FPGAs The Xilinx Virtex series was the first line of FPGAs to offer one million system gates. Introduced in 1998, the Virtex product line fundamentally redefined programmable logic by expanding the traditional capabilities of FPGAs to include a powerful set of features that address board level problems for high performance system designs. The latest devices in the Virtex-E series, unveiled in 1999, offer more than three million system gates. Virtex-EM devices, introduced in 2000 and the first FPGAs to be manufactured using an advanced copper process, offer additional on-chip memory for network switch applications Xilinx • 24
. XILINX SOLUTIONS FIGURE 2-2: PLATFORM FPGAS Spartan FPGAs Xilinx Spartan FPGAs are ideal for low-cost, high-volume applications and are targeted as replacements for fixed-logic gate arrays and ASSP products such as bus interface chip sets. The five members of the family are the Spartan-3 (1.2V), Spartan-IIE (1.8V), Spartan-II (2.5V), Spartan XL (3.3V), and Spartan (5V) devices. SPARTAN-3 FPGAS The Spartan-3 (1.2V, 90 nm) FPGA is not only available for a very low cost, but it integrates many architectural features associated with high-end programmable logic. This combination of low cost and features makes it an ideal replacement for ASICs (gate arrays) and many ASSP devices. For example, a Spartan-3 FPGA in a car multimedia system could absorb many system functions, including embedded IP cores, custom system interfaces, DSP, and logic. The diagram below shows such a system: Xilinx • 25
Page 1 and 2: Programmable Logic Design Quick Sta
Page 3 and 4: ABSTRACT Whether you design with di
Page 5 and 6: NAVIGATING THIS BOOK C HAPTER 5: IM
Page 7 and 8: TABLE OF CONTENTS Virtex FPGAs.....
Page 9 and 10: TABLE OF CONTENTS MicroBlaze and Pi
Page 11 and 12: Chapter 7: Design Reference Bank TA
Page 13 and 14: C HAPTER 1 Introduction The History
Page 15 and 16: INTRODUCTION Other architectures fo
Page 17 and 18: INTRODUCTION vides an instant hardw
Page 19 and 20: INTRODUCTION FIGURE 1-4: FPGA ARCHI
Page 21 and 22: INTRODUCTION By using Xilinx CoolRu
Page 23 and 24: INTRODUCTION FIGURE 1-8: DESIGN SPE
Page 25 and 26: INTRODUCTION For the HDL specificat
Page 27 and 28: INTRODUCTION Even if you decide to
Page 29 and 30: INTRODUCTION original I/O pin place
Page 31 and 32: INTRODUCTION FIGURE 1-11: DEVICE IM
Page 33 and 34: C HAPTER 2 Xilinx Solutions Introdu
Page 35: XILINX SOLUTIONS The Platform FPGA
Page 39 and 40: XILINX SOLUTIONS FIGURE 2-4: SPARTA
Page 41 and 42: XILINX SOLUTIONS • Full- and half
Page 43 and 44: TABLE 2-3: SPARTAN-3 FEATURES AND B
Page 49 and 50: XILINX SOLUTIONS FIGURE 2-10: SPART
Page 51 and 52: Delay-Locked Loop XILINX SOLUTIONS
Page 53 and 54: XILINX SOLUTIONS FIGURE 2-15: SPART
Page 55 and 56: XILINX SOLUTIONS Low Power - Is you
Page 57 and 58: XILINX SOLUTIONS XC9500XL family is
Page 59 and 60: XILINX SOLUTIONS TABLE 2-5: XC9500X
Page 61 and 62: XILINX SOLUTIONS caded chain of pur
Page 63 and 64: XILINX SOLUTIONS FIGURE 2-22: COOLR
Page 65 and 66: I/O Cell XILINX SOLUTIONS The outpu
Page 67 and 68: TABLE 2-6: VFM (Variable Function M
Page 69 and 70: XILINX SOLUTIONS Figure 2-27 also d
Page 71 and 72: XILINX SOLUTIONS At the high level,
Page 73 and 74: XILINX SOLUTIONS FIGURE 2-30: COOLR
Page 75 and 76: XILINX SOLUTIONS The larger parts (
Page 77 and 78: XILINX SOLUTIONS Note that a synchr
Page 79 and 80: XILINX SOLUTIONS These security bit
Page 81 and 82: XILINX SOLUTIONS COOLRUNNER REFEREN
Page 83 and 84: . XILINX SOLUTIONS FIGURE 2-42: LOG
Page 85 and 86: XILINX SOLUTIONS To address the nee
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XILINX SOLUTIONS This rich mixture
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Dynamic Verification XILINX SOLUTIO
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XILINX SOLUTIONS Xilinx IP Cores Th
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XILINX SOLUTIONS • Test and Measu
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XILINX SOLUTIONS be fixed, upgraded
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XILINX SOLUTIONS TABLE 2-10: XILINX
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XILINX SOLUTIONS CONNECTIVITY CENTR
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XILINX SOLUTIONS design • Broad a
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Xilinx Student Edition Frequently A
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C HAPTER 3 WebPACK ISE Design Softw
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WEBPACK ISE DESIGN SOFTWARE 4. Gene
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WEBPACK ISE DESIGN SOFTWARE WEBPACK
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Summary PROJECTS WEBPACK ISE DESIGN
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C HAPTER 4 WebPACK ISE Design Entry
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WEBPACK ISE DESIGN ENTRY FIGURE 4-2
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WEBPACK ISE DESIGN ENTRY Notice tha
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WEBPACK ISE DESIGN ENTRY As you hav
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WEBPACK ISE DESIGN ENTRY The area s
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WEBPACK ISE DESIGN ENTRY Click OK t
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WEBPACK ISE DESIGN ENTRY Maximize t
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WEBPACK ISE DESIGN ENTRY Open the S
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WEBPACK ISE DESIGN ENTRY Set RD to
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WEBPACK ISE DESIGN ENTRY In the edi
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Click on the Generate HDL button on
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WEBPACK ISE DESIGN ENTRY Click on t
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WEBPACK ISE DESIGN ENTRY Connect th
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You are now ready to go to the impl
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WEBPACK ISE DESIGN ENTRY Move the c
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Your completed schematic should loo
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C HAPTER 5 Implementing CPLDs Intro
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IMPLEMENTING CPLDS The design shoul
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IMPLEMENTING CPLDS Notice that the
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DoubLe-click in the Period window o
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IMPLEMENTING CPLDS In the Clock to
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IMPLEMENTING CPLDS Click on the “
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IMPLEMENTING CPLDS To open the CPLD
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IMPLEMENTING CPLDS MXE will open, b
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C HAPTER 6 Implementing FPGAs Intro
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IMPLEMENTING FPGAS Double-click on
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IMPLEMENTING FPGAS The FSM encoding
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IMPLEMENTING FPGAS The Constraints
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IMPLEMENTING FPGAS Highlight the th
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IMPLEMENTING FPGAS Save and close t
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IMPLEMENTING FPGAS Programming Righ
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C HAPTER 7 Design Reference Bank In
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DESIGN REFERENCE BANK A high-powere
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DESIGN REFERENCE BANK USING A MICRO
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DESIGN REFERENCE BANK port ( clk :
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DESIGN REFERENCE BANK vated, it wil
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DESIGN REFERENCE BANK Figure 7-7 sh
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DESIGN REFERENCE BANK Full-function
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DESIGN REFERENCE BANK TABLE 7-1: DO
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DESIGN REFERENCE BANK TABLE 7-1: DO
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ACRONYMS ABEL ADC AIM ANSI ASIC ASS
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ACRONYMS LVDS Low Voltage Different
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PROGRAMMABLE LOGIC DESIGN -- QUICK
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