Programmable Logic Design Quick Start Handbook
Programmable Logic Design Quick Start Handbook
Programmable Logic Design Quick Start Handbook
You also want an ePaper? Increase the reach of your titles
YUMPU automatically turns print PDFs into web optimized ePapers that Google loves.
PROGRAMMABLE LOGIC DESIGN: QUICK START HANDBOOK • CHAPTER 1<br />
Xilinx • 16<br />
Functional Simulation<br />
At this point in the design flow, a functional simulation only checks that the<br />
circuits give the right combinations of ones and zeros. You would conduct a timing<br />
simulation a little later in the design flow.<br />
If there are any problems, you can go back to the schematic or HDL file,<br />
make changes, re-generate the netlist, and then rerun the simulation. <strong>Design</strong>ers<br />
typically spend 50% of their development time going through this loop until the<br />
design works as required.<br />
Using HDL offers an additional advantage when verifying the design: You<br />
can simulate directly from the HDL source file. This bypasses the time-consuming<br />
synthesis process that would normally be required for every design change<br />
iteration.<br />
Once the circuit works correctly, running the synthesis tool generates the<br />
netlist for the next step in the design flow – device implementation.<br />
Device Implementation<br />
A design netlist completely describes the design using the gates for a specific<br />
vendor/device family. Once it’s fully verified, it’s time to put this in a chip,<br />
referred to as device implementation.<br />
Translate comprises various programs used to import the design netlist and<br />
prepare it for layout. The programs will vary among vendors.<br />
Some of the more common programs during translate include: optimization,<br />
translation to the physical device elements, and device-specific design rule<br />
checking (e.g,. does the design exceed the number of clock buffers available in<br />
this device).<br />
During the stage of the design flow, you will be asked to select the target<br />
device, package, speed grade, and any other device-specific options.<br />
The translate step usually ends with a comprehensive report of the results<br />
of all the programs executed. In addition to warnings and errors is usually a listing<br />
of device and I/O utilization, which helps you to determine if you’ve<br />
selected the best device.<br />
Fitting<br />
For CPLDs, the design step is called fitting, meaning to “fit” the design to<br />
the target device. In the diagram above, a section of the design is fit to the CPLD.<br />
CPLDs are a fixed architecture, so the software needs to pick the gates and<br />
interconnect paths that match the circuit. This is usually a fast process.<br />
The biggest potential problem is if you had previously assigned the exact<br />
locations of the I/O pins, commonly referred to as pin locking. Most often, this<br />
occurs when using a legacy design iteration that has been committed to the<br />
printed circuit board layout.<br />
Architectures that support I/O pin locking (such as the Xilinx XC9500 and<br />
CoolRunner CPLDs) have a very big advantage. They allow you to keep the