Programmable Logic Design Quick Start Handbook

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PROGRAMMABLE LOGIC DESIGN: QUICK START HANDBOOK • CHAPTER 1 Xilinx • 16 Functional Simulation At this point in the design flow, a functional simulation only checks that the circuits give the right combinations of ones and zeros. You would conduct a timing simulation a little later in the design flow. If there are any problems, you can go back to the schematic or HDL file, make changes, re-generate the netlist, and then rerun the simulation. <strong>Design</strong>ers typically spend 50% of their development time going through this loop until the design works as required. Using HDL offers an additional advantage when verifying the design: You can simulate directly from the HDL source file. This bypasses the time-consuming synthesis process that would normally be required for every design change iteration. Once the circuit works correctly, running the synthesis tool generates the netlist for the next step in the design flow – device implementation. Device Implementation A design netlist completely describes the design using the gates for a specific vendor/device family. Once it’s fully verified, it’s time to put this in a chip, referred to as device implementation. Translate comprises various programs used to import the design netlist and prepare it for layout. The programs will vary among vendors. Some of the more common programs during translate include: optimization, translation to the physical device elements, and device-specific design rule checking (e.g,. does the design exceed the number of clock buffers available in this device). During the stage of the design flow, you will be asked to select the target device, package, speed grade, and any other device-specific options. The translate step usually ends with a comprehensive report of the results of all the programs executed. In addition to warnings and errors is usually a listing of device and I/O utilization, which helps you to determine if you’ve selected the best device. Fitting For CPLDs, the design step is called fitting, meaning to “fit” the design to the target device. In the diagram above, a section of the design is fit to the CPLD. CPLDs are a fixed architecture, so the software needs to pick the gates and interconnect paths that match the circuit. This is usually a fast process. The biggest potential problem is if you had previously assigned the exact locations of the I/O pins, commonly referred to as pin locking. Most often, this occurs when using a legacy design iteration that has been committed to the printed circuit board layout. Architectures that support I/O pin locking (such as the Xilinx XC9500 and CoolRunner CPLDs) have a very big advantage. They allow you to keep the
INTRODUCTION original I/O pin placements regardless of the number of design changes, utilization, or required performance. Pin locking is very important when using ISP. If you layout your PCB to accept a specific pin out, and then change the design, you can re-program confident that you pin out will stay the same. Place and Route For FPGAs, place and route programs are run after compile. “Place” is the process of selecting specific modules, or logic blocks, in the FPGAs where design gates will reside. “Route,” as the name implies, is the physical routing of the interconnect between the logic blocks. Most vendors provide automatic place and route tools so that you don’t have to worry about the intricate details of the device architecture. Some vendors offer tools that allow expert users to manually place and/or route the most critical parts of their designs to achieve better performance than with the automatic tools. Floorplanner is a type of manual tool. Place and route programs require the longest time to complete successfully because it’s a complex task to determine the location of large designs, ensure that they all get connected correctly, and meet the desired performance. These programs however, can only work well if the target architecture has sufficient routing for the design. No amount of fancy coding can compensate for an ill-conceived architecture, especially if there are not enough routing tracks. If you were to encounter this problem, the most common solution would be to use a larger device. And you would likely remember the experience the next time you selected a vendor. A related program is called timing-driven place and route (TDPR). This allows you to specify timing criteria that will be used during device layout. A static timing analyzer is usually part of the vendor’s implementation software. It provides timing information about paths in the design. This information is very accurate and can be viewed in many different ways, such as displaying all paths in the design and ranking them from longest to shortest delay. In addition, at this point you can use the detailed layout information after reformatting and go back to your chosen simulator with detailed timing information. This process is called back-annotation and has the advantage of providing the accurate timing as well as the zeros and ones operation of your design. In both cases, the timing reflects delays of the logic blocks as well as the interconnect. The final implementation step is the download or program. Xilinx • 17
Page 1 and 2: Programmable Logic Design Quick Sta
Page 3 and 4: ABSTRACT Whether you design with di
Page 5 and 6: NAVIGATING THIS BOOK C HAPTER 5: IM
Page 7 and 8: TABLE OF CONTENTS Virtex FPGAs.....
Page 9 and 10: TABLE OF CONTENTS MicroBlaze and Pi
Page 11 and 12: Chapter 7: Design Reference Bank TA
Page 13 and 14: C HAPTER 1 Introduction The History
Page 15 and 16: INTRODUCTION Other architectures fo
Page 17 and 18: INTRODUCTION vides an instant hardw
Page 19 and 20: INTRODUCTION FIGURE 1-4: FPGA ARCHI
Page 21 and 22: INTRODUCTION By using Xilinx CoolRu
Page 23 and 24: INTRODUCTION FIGURE 1-8: DESIGN SPE
Page 25 and 26: INTRODUCTION For the HDL specificat
Page 27: INTRODUCTION Even if you decide to
Page 31 and 32: INTRODUCTION FIGURE 1-11: DEVICE IM
Page 33 and 34: C HAPTER 2 Xilinx Solutions Introdu
Page 35 and 36: XILINX SOLUTIONS The Platform FPGA
Page 37 and 38: . XILINX SOLUTIONS FIGURE 2-2: PLAT
Page 39 and 40: XILINX SOLUTIONS FIGURE 2-4: SPARTA
Page 41 and 42: XILINX SOLUTIONS • Full- and half
Page 43 and 44: TABLE 2-3: SPARTAN-3 FEATURES AND B
Page 49 and 50: XILINX SOLUTIONS FIGURE 2-10: SPART
Page 51 and 52: Delay-Locked Loop XILINX SOLUTIONS
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Page 55 and 56: XILINX SOLUTIONS Low Power - Is you
Page 57 and 58: XILINX SOLUTIONS XC9500XL family is
Page 59 and 60: XILINX SOLUTIONS TABLE 2-5: XC9500X
Page 61 and 62: XILINX SOLUTIONS caded chain of pur
Page 63 and 64: XILINX SOLUTIONS FIGURE 2-22: COOLR
Page 65 and 66: I/O Cell XILINX SOLUTIONS The outpu
Page 67 and 68: TABLE 2-6: VFM (Variable Function M
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Page 71 and 72: XILINX SOLUTIONS At the high level,
Page 73 and 74: XILINX SOLUTIONS FIGURE 2-30: COOLR
Page 75 and 76: XILINX SOLUTIONS The larger parts (
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XILINX SOLUTIONS These security bit
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XILINX SOLUTIONS COOLRUNNER REFEREN
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. XILINX SOLUTIONS FIGURE 2-42: LOG
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XILINX SOLUTIONS To address the nee
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XILINX SOLUTIONS This rich mixture
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Dynamic Verification XILINX SOLUTIO
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XILINX SOLUTIONS Xilinx IP Cores Th
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XILINX SOLUTIONS • Test and Measu
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XILINX SOLUTIONS be fixed, upgraded
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XILINX SOLUTIONS TABLE 2-10: XILINX
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XILINX SOLUTIONS CONNECTIVITY CENTR
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XILINX SOLUTIONS design • Broad a
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Xilinx Student Edition Frequently A
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C HAPTER 3 WebPACK ISE Design Softw
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WEBPACK ISE DESIGN SOFTWARE 4. Gene
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WEBPACK ISE DESIGN SOFTWARE WEBPACK
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Summary PROJECTS WEBPACK ISE DESIGN
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C HAPTER 4 WebPACK ISE Design Entry
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WEBPACK ISE DESIGN ENTRY FIGURE 4-2
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WEBPACK ISE DESIGN ENTRY Notice tha
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WEBPACK ISE DESIGN ENTRY As you hav
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WEBPACK ISE DESIGN ENTRY The area s
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WEBPACK ISE DESIGN ENTRY Click OK t
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WEBPACK ISE DESIGN ENTRY Maximize t
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WEBPACK ISE DESIGN ENTRY Open the S
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WEBPACK ISE DESIGN ENTRY Set RD to
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WEBPACK ISE DESIGN ENTRY In the edi
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Click on the Generate HDL button on
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WEBPACK ISE DESIGN ENTRY Click on t
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WEBPACK ISE DESIGN ENTRY Connect th
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You are now ready to go to the impl
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WEBPACK ISE DESIGN ENTRY Move the c
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Your completed schematic should loo
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C HAPTER 5 Implementing CPLDs Intro
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IMPLEMENTING CPLDS The design shoul
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IMPLEMENTING CPLDS Notice that the
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DoubLe-click in the Period window o
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IMPLEMENTING CPLDS In the Clock to
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IMPLEMENTING CPLDS Click on the “
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IMPLEMENTING CPLDS To open the CPLD
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IMPLEMENTING CPLDS MXE will open, b
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C HAPTER 6 Implementing FPGAs Intro
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IMPLEMENTING FPGAS Double-click on
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IMPLEMENTING FPGAS The FSM encoding
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IMPLEMENTING FPGAS The Constraints
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IMPLEMENTING FPGAS Highlight the th
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IMPLEMENTING FPGAS Save and close t
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IMPLEMENTING FPGAS Programming Righ
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C HAPTER 7 Design Reference Bank In
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DESIGN REFERENCE BANK A high-powere
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DESIGN REFERENCE BANK USING A MICRO
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DESIGN REFERENCE BANK port ( clk :
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DESIGN REFERENCE BANK vated, it wil
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DESIGN REFERENCE BANK Figure 7-7 sh
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DESIGN REFERENCE BANK Full-function
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DESIGN REFERENCE BANK TABLE 7-1: DO
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DESIGN REFERENCE BANK TABLE 7-1: DO
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ACRONYMS ABEL ADC AIM ANSI ASIC ASS
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ACRONYMS LVDS Low Voltage Different
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PROGRAMMABLE LOGIC DESIGN -- QUICK
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