Programmable Logic Design Quick Start Handbook
Programmable Logic Design Quick Start Handbook
Programmable Logic Design Quick Start Handbook
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PROGRAMMABLE LOGIC DESIGN: QUICK START HANDBOOK • CHAPTER 1<br />
using the best gate configuration to minimize power, or using the FPGAfriendly,<br />
register-rich configuration for state machines.<br />
You can easily experiment with different vendors, device families, and optimization<br />
constraints, thus exploring many different solutions instead of just one<br />
with the schematic approach.<br />
To recap, the advantages of high level design and synthesis are many. It is<br />
much simpler and faster to specify your design using HLD, and much easier to<br />
make changes to the design because of the self-documenting nature of the language.<br />
You are relieved from the tedium of selecting and interconnecting at the<br />
gate level. Merely select the library and optimization criteria (e.g., speed, area)<br />
and the synthesis tool will determine the results.<br />
You can also try different design alternatives and select the best one for the<br />
application. In fact, there is no real practical alternative for designs exceeding<br />
10,000 gates.<br />
Intellectual Property (IP) Cores<br />
IP cores are very complex pre-tested system-level functions that are used in<br />
logic designs to dramatically shorten development time.<br />
The benefits of using an IP core include:<br />
• Faster time to market<br />
• A simplified development process<br />
• Minimal design risk<br />
• Reduced software compile time<br />
• Reduced verification time<br />
• Predictable performance/functionality.<br />
IP cores are similar to vendor-provided soft macros in that they simplify the<br />
design specification step by removing designers from gate-level details of commonly<br />
used functions.<br />
IP cores differ from soft macros in that they are generally much larger system-level<br />
functions, such as a PCI bus interface, DSP filter, or PCMCIA interface.<br />
They are extensively tested (and hence rarely free of charge) to prevent<br />
designers from having to verify the IP core functions themselves.<br />
<strong>Design</strong> Verification<br />
<strong>Programmable</strong> logic designs are verified by using a simulator, which is a<br />
software program that confirms the functionality or timing of a circuit.<br />
The industry-standard formats used ensure that designs can be reused. If a<br />
vendors changes its libraries, only a synthesis recompile is necessary.<br />
Xilinx • 14