Programmable Logic Design Quick Start Handbook

PROGRAMMABLE LOGIC DESIGN: QUICK START HANDBOOK • CHAPTER 1
As an example, let’s design a 16 x 16 multiplier specified with a schematic
capture and an HDL file.
A multiplier is a regular but complex arrangement of adders and registers
that requires quite a few gates. Our example has two 16-bit inputs (A and B) and
a 32-bit product output (Y = A x B) – that’s a total of 64 I/Os. This circuit requires
approximately 6,000 equivalent gates.
In the schematic implementation, the required gates would have to be
loaded, positioned on the page, and interconnected, with I/O buffers added.
That’s about three days’ worth of work.
The HDL implementation, which is also 6,000 gates, requires eight lines of
text and can be done in three minutes. This file contains all the information necessary
to define our 16 x 16 multiplier.
So, as a designer, which method would you choose In addition to the tremendous
time savings, the HDL method is completely vendor-independent.
This opens up tremendous design possibilities for engineers.
FIGURE 1-9:
DESIGN SPECIFICATION – MULTIPLIER
To create a 32 x 32 multiplier, you could simply modify the work you’d
already done for the smaller multiplier.
For the schematic approach, this would entail making three copies of the 30
pages, then figuring out where to edit the 90 pages so that they addressed the
larger bus widths. This would probably require four hours of graphical editing.
Xilinx • 12