Programmable Logic Design Quick Start Handbook

PROGRAMMABLE LOGIC DESIGN: QUICK START HANDBOOK • CHAPTER 1
3. Add and label the input and output buffers. These will define the I/O
package pins for the device.
4. Generate a netlist.
FIGURE 1-7:
PLD DESIGN FLOW
A netlist is a text equivalent of the circuit. It is generated by design tools
such as a schematic capture program. The netlist is a compact way for other programs
to understand what gates are in the circuit, how they are connected, and
the names of the I/O pins.
In the example below, the netlist reflects the actual syntax of the circuit in
the schematic. There is one line for each of the components and one line for each
of the nets. Note that the computer assigns names to components (G1 to G4) and
to the nets (N1 to N8). When implementing this design, it will have input package
pins A, B, C, and D, and output pins Q, R, and S.
EDIF is the industry-wide standard for netlists; many others exist, including
vendor-specific ones such as the Xilinx Netlist Format (XNF).
Once you have the design netlist, you have all you need to determine what
the circuit does.
Xilinx • 10