Programmable Logic Design Quick Start Handbook

PROGRAMMABLE LOGIC DESIGN -- QUICK START HANDBOOK •
Pin-Locking – Rigidly defining and maintaining the functionality and timing
requirements of device pins while the internal logic is still being designed or
modified. Pin-locking has become important, since circuit-board fabrication
times are longer than PLD design implementation times.
PIP – Programmable Interconnect Point. In Xilinx FPGAs, a point where
two signal lines can be connected, as determined by the device configuration.
Placement – In FPGAs, the process of assigning specific parts of the design
to specific locations (CLBs) on the chip. Usually done automatically.
PLA – Programmable Logic Array. The first and most flexible programmable
logic configuration with two programmable planes providing any combination
of “AND” and “OR” gates and sharing of AND terms across multiple ORs.
This architecture is implemented in CoolRunner and CoolRunner-II devices.
PLD – Programmable Logic Device. Most generic name for all programmable
logic: PALs, CPLDs, and FPGAs.
QML – Qualified Manufacturing Line. For example, ISO9000.
Routing – The interconnection, or the process of creating the desired interconnection,
of logic cells to make them perform the desired function. Routing
follows partitioning and placement.
Schematic – Graphic representation of a logic design in the form of interconnected
gates, flip-flops, and larger blocks. Older and more visually intuitive
alternative to the increasingly more popular equation-based or high-level language
text description of a logic design.
SelectRAM – Xilinx-specific name for a small RAM (usually 16 bits), implemented
in a LUT.
Simulation – Computer modeling of logic and (sometimes) timing behavior
of logic driven by simulation inputs (stimuli or vectors).
SPROM – Serial Programmable Read-Only Memory. Non-volatile memory
device that can store the FPGA configuration bitstream. The SPROM has a
built-in address counter, receives a clock, and outputs a serial bitstream.
SRAM – Static Random Access Memory. Read-write memory with data
stored in latches. Faster than DRAM and with simpler timing requirements, but
smaller in size and about four times as expensive than DRAM of the same
capacity.
SRL16 – Shift Register LUT, an alternative mode of operation for every
function generator (LUT) that are part of every CLB in Virtex and Spartan
FPGAs. This mode increases the number of flip-flops by 16. Adding flip-flops
enables fast pipelining – ideal in DSP applications.
Static Timing – Detailed description of on-chip logic and interconnect
delays.
Sub-Micron – The smallest feature size is usually expressed in micron (µ =
millionth of a meter, or thousandth of a millimeter) The state of the art is moving
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