Programmable Logic Design Quick Start Handbook

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PROGRAMMABLE LOGIC DESIGN -- QUICK START HANDBOOK • Xilinx • 186 Footprint – The printed circuit pattern that accepts a device and connects its pins appropriately. Footprint-compatible devices can be interchanged without modifying the PC board. FPGA – Field Programmable Gate Array. An integrated circuit that contains configurable (programmable) logic blocks and configurable (programmable) interconnect between those blocks. Function Generator – Also called look-up-table, with N-inputs and one output. Can implement any logic function of its N-inputs. N is between 2 and 6; 4-input function generators are most popular. GAL – Generic Array Logic. Lattice name for a variation on PALs Gate. Smallest logic element with several inputs and one output. AND gate output is high when all inputs are high. OR gate output is high when at least one input is high. A 2-input NAND gate is used as the measurement unit for gate array complexity. Gate Array – ASIC where transistors are pre-defined, and only the interconnect pattern is customized for the individual application. GTL – Gunning Transceiver Logic. A high-speed, low-power back-plane standard. GUI – Graphic User Interface. A way of representing the computer output on the screen as graphics, pictures, icons, and windows. Pioneered by Xerox and the Macintosh, now universally adopted (e.g., by Windows 95). HDL – Hardware Description Language. Hierarchical Design – Design description in multiple layers, from the highest (overview) to the lowest (circuit details). Alternative: flat design, where everything is described at the same level of detail. Incremental design making small design changes while maintaining most of the layout and routing. Interconnect – Metal lines and programmable switches that connect signals between logic blocks and between logic blocks and the I/O. IOB or I/O – Input/Output block. Logic block with features specialized for interfacing with the PC board. ISO9000 – An internationally recognized quality standard. Xilinx is certified to ISO9001 and ISO9002. IP – Intellectual Property. In the legal sense: patents, copyrights, and trade secrets. In integrated circuits: pre-defined large functions, called cores, that help you complete large designs faster. IQ – Extended temperature devices for automotive and industrial applications. ISP – In-System Programmable device. A programmable logic device that can be programmed after it has been connected to (soldered into) the system PC board. Although all SRAM-based FPGAs are naturally ISP, this term is only used with certain CPLDs, to distinguish them from the older CPLDs that must be programmed in programming equipment.
GLOSSARY OF TERMS JTAG – Joint Test Action Group. Older name for IEEE 1149.1 Boundary Scan, a method to test PC boards and ICs. LogiBLOX – Formerly called X-Blox. Library of logic modules, often with user-definable parameters, like data width. Very similar to LPM. Logic Cell – Metric for FPGA density. One logic cell is one 4-input look-up table plus one flip-flop. LPM – Library of Parameterized Modules. Library of logic modules, often with user-definable parameters, like data width. Very similar to LogiBlox. LUT – Look-Up Table. Also called function generator with N inputs and one output. Can implement any logic function of its N inputs. N is between 2 and 6; 4-input LUTs are most popular. Macrocell – The logic cell in a sum-of-products CPLD or PAL/GAL. Mapping – Process of assigning portions of the logic design to the physical chip resources (CLBs). With FPGAs, mapping is a more demanding and more important process than with gate arrays. MTBF – Mean Time Between Failure. The statistically relevant up-time between equipment failure. See also FIT. Netlist – Textual description of logic and interconnects. See also XNF and EDIF. NRE – Non-Recurring Engineering charges. Startup cost for the creation of an ASIC, gate array, or HardWire. Pays for layout, masks, and test development. FPGAs and CPLDs do not require NRE. Optimization – Design change to improve performance. See also Synthesis. OTP – One-Time Programmable. Irreversible method of programming logic or memory. Fuses and anti-fuses are inherently OTP. EPROMs and EPROM-based CPLDs are OTP if their plastic package blocks the ultraviolet light needed to erase the stored data or configuration. PAL – Programmable Array Logic. Oldest practical form of programmable logic, implemented a sum-of-products plus optional output flip-flops. Partitioning – In FPGAs, the process of dividing the logic into sub-functions that can later be placed into individual CLBs. Partitioning precedes placement. PCI – Peripheral Component Interface. Synchronous bus standard characterized by short range, light loading, low cost, and high performance. A 33 MHz PCI can support data byte transfers of up to 132 megabytes per second on 36 parallel data lines (including parity) and a common clock. There is also a new 66 MHz standard. PCMCIA – Personal Computer Memory Card Interface Association. (Also: People Can’t Memorize Computer Industry Acronyms). Physical and electrical standard for small plug-in boards for portable computers. Xilinx • 187
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Programmable Logic Design Quick Sta
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ABSTRACT Whether you design with di
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NAVIGATING THIS BOOK C HAPTER 5: IM
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TABLE OF CONTENTS Virtex FPGAs.....
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TABLE OF CONTENTS MicroBlaze and Pi
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Chapter 7: Design Reference Bank TA
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C HAPTER 1 Introduction The History
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INTRODUCTION Other architectures fo
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INTRODUCTION vides an instant hardw
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INTRODUCTION FIGURE 1-4: FPGA ARCHI
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INTRODUCTION By using Xilinx CoolRu
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INTRODUCTION FIGURE 1-8: DESIGN SPE
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INTRODUCTION For the HDL specificat
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INTRODUCTION Even if you decide to
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INTRODUCTION original I/O pin place
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INTRODUCTION FIGURE 1-11: DEVICE IM
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C HAPTER 2 Xilinx Solutions Introdu
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XILINX SOLUTIONS The Platform FPGA
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. XILINX SOLUTIONS FIGURE 2-2: PLAT
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XILINX SOLUTIONS FIGURE 2-4: SPARTA
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XILINX SOLUTIONS • Full- and half
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TABLE 2-3: SPARTAN-3 FEATURES AND B
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XILINX SOLUTIONS FIGURE 2-10: SPART
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Delay-Locked Loop XILINX SOLUTIONS
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XILINX SOLUTIONS FIGURE 2-15: SPART
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XILINX SOLUTIONS Low Power - Is you
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XILINX SOLUTIONS XC9500XL family is
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XILINX SOLUTIONS TABLE 2-5: XC9500X
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XILINX SOLUTIONS caded chain of pur
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XILINX SOLUTIONS FIGURE 2-22: COOLR
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I/O Cell XILINX SOLUTIONS The outpu
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TABLE 2-6: VFM (Variable Function M
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XILINX SOLUTIONS Figure 2-27 also d
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XILINX SOLUTIONS At the high level,
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XILINX SOLUTIONS FIGURE 2-30: COOLR
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XILINX SOLUTIONS The larger parts (
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XILINX SOLUTIONS Note that a synchr
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XILINX SOLUTIONS These security bit
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XILINX SOLUTIONS COOLRUNNER REFEREN
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. XILINX SOLUTIONS FIGURE 2-42: LOG
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XILINX SOLUTIONS To address the nee
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XILINX SOLUTIONS This rich mixture
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Dynamic Verification XILINX SOLUTIO
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XILINX SOLUTIONS Xilinx IP Cores Th
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XILINX SOLUTIONS • Test and Measu
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XILINX SOLUTIONS be fixed, upgraded
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XILINX SOLUTIONS TABLE 2-10: XILINX
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XILINX SOLUTIONS CONNECTIVITY CENTR
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XILINX SOLUTIONS design • Broad a
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Xilinx Student Edition Frequently A
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C HAPTER 3 WebPACK ISE Design Softw
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WEBPACK ISE DESIGN SOFTWARE 4. Gene
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WEBPACK ISE DESIGN SOFTWARE WEBPACK
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Summary PROJECTS WEBPACK ISE DESIGN
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C HAPTER 4 WebPACK ISE Design Entry
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WEBPACK ISE DESIGN ENTRY FIGURE 4-2
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WEBPACK ISE DESIGN ENTRY Notice tha
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WEBPACK ISE DESIGN ENTRY As you hav
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WEBPACK ISE DESIGN ENTRY The area s
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WEBPACK ISE DESIGN ENTRY Click OK t
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WEBPACK ISE DESIGN ENTRY Maximize t
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WEBPACK ISE DESIGN ENTRY Open the S
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WEBPACK ISE DESIGN ENTRY Set RD to
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WEBPACK ISE DESIGN ENTRY In the edi
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Click on the Generate HDL button on
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WEBPACK ISE DESIGN ENTRY Click on t
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WEBPACK ISE DESIGN ENTRY Connect th
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You are now ready to go to the impl
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WEBPACK ISE DESIGN ENTRY Move the c
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Your completed schematic should loo
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C HAPTER 5 Implementing CPLDs Intro
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IMPLEMENTING CPLDS The design shoul
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IMPLEMENTING CPLDS Notice that the
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Programmable Logic Design Quick Start Handbook

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