Programmable Logic Design Quick Start Handbook
Programmable Logic Design Quick Start Handbook
Programmable Logic Design Quick Start Handbook
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Glossary of Terms<br />
GLOSSARY OF TERMS<br />
ABEL – Advanced Boolean Expression Language, low-level language for<br />
design entry, from Data I/O.<br />
AIM – Advanced Interconnect Matrix in the CoolRunner-II CPLD that provides<br />
the flexible interconnection between the PLA function blocks.<br />
Antifuse – A small circuit element that can be irreversibly changed from<br />
being non-conducting to being conducting with ~100 Ohm. Anti-fuse-based<br />
FPGAs are thus non-volatile and can be programmed only once (see OTP).<br />
AQL – Acceptable Quality Level. The relative number of devices, expressed<br />
in parts-per-million (ppm), that might not meet specification or be defective.<br />
Typical values are around 10 ppm.<br />
ASIC – Application Specific Integrated Circuit, also called a gate array.<br />
Asynchronous logic that is not synchronized by a clock. Asynchronous designs<br />
can be faster than synchronous ones, but are more sensitive to parametric<br />
changes and are thus less robust.<br />
ASSP – Application-Specific Standard Product. Type of high-integration<br />
chip or chipset ASIC that is designed for a common yet specific application.<br />
ATM – Asynchronous Transfer Mode. A very high-speed (megahertz to<br />
gigahertz) connection-oriented bit-serial protocol for transmitting data and realtime<br />
voice and video in fixed-length packets (48-byte payload, 5-byte header).<br />
Back Annotation – Automatically attaching timing values to the entered<br />
design format after the design has been placed and routed in an FPGA.<br />
Behavioral Language – Top-down description from an even higher level<br />
than VHDL.<br />
Block RAM – A block of 2k to 4k bits of RAM inside an FPGA. Dual-port<br />
and synchronous operation are desirable.<br />
CAD – Computer Aided <strong>Design</strong>, using computers to design products.<br />
CAE – Computer Aided Engineering, analyses designs created on a computer.<br />
CLB – Configurable <strong>Logic</strong> Block. Xilinx-specific name for a block of logic<br />
surrounded by routing resources. A CLB contains two or four LUTs (function<br />
generators) plus two or four flip-flops.<br />
CMOS – Complementary Metal-Oxide-Silicon. Dominant technology for<br />
logic and memory. Has replaced the older bipolar TTL technology in most<br />
applications (except very fast ones). CMOS offers lower power consumption<br />
and smaller chip sizes compared to bipolar and now meets or even beats TTL<br />
speed.<br />
Xilinx • 183