Programmable Logic Design Quick Start Handbook

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PROGRAMMABLE LOGIC DESIGN -- QUICK START HANDBOOK • CHAPTER 6 Xilinx • 160
C HAPTER 7 <strong>Design</strong> Reference Bank Introduction Our final chapter contains a useful list of design examples and applications that will give you a good jump start into your future programmable logic designs. We selected the application examples from a comprehensive list of application notes available from the Xilinx website, as well as extracts from the Xilinx quarterly magazine, the Xcell Journal (To subscribe, click on “Subscribe to Xcell Journal” at www.xilinx.com/publications/xcellonline/). This section will also give you pointers on where to look for and download code and search for IP from the Xilinx website. Get the Most out of Microcontroller-Based <strong>Design</strong>s Microcontrollers don’t make the world go round, but they most certainly help us get around in the world. You can find microcontrollers in automobiles, microwave ovens, automatic teller machines, VCRs, point-of-sale terminals, robotic devices, wireless telephones, home security systems, and satellites, to name just a few applications. In the never-ending quest for faster, better, and cheaper products, advanced designers are now pairing CPLDs with microcontrollers to take advantage of the strengths of each. Microcontrollers are naturally good at sequential processes and computationally intensive tasks, as well as a host of non-time-critical tasks.
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Programmable Logic Design Quick Sta
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ABSTRACT Whether you design with di
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NAVIGATING THIS BOOK C HAPTER 5: IM
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TABLE OF CONTENTS Virtex FPGAs.....
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TABLE OF CONTENTS MicroBlaze and Pi
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Chapter 7: Design Reference Bank TA
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C HAPTER 1 Introduction The History
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INTRODUCTION Other architectures fo
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INTRODUCTION vides an instant hardw
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INTRODUCTION FIGURE 1-4: FPGA ARCHI
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INTRODUCTION By using Xilinx CoolRu
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INTRODUCTION FIGURE 1-8: DESIGN SPE
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INTRODUCTION For the HDL specificat
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INTRODUCTION Even if you decide to
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INTRODUCTION original I/O pin place
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INTRODUCTION FIGURE 1-11: DEVICE IM
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C HAPTER 2 Xilinx Solutions Introdu
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XILINX SOLUTIONS The Platform FPGA
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. XILINX SOLUTIONS FIGURE 2-2: PLAT
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XILINX SOLUTIONS FIGURE 2-4: SPARTA
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XILINX SOLUTIONS • Full- and half
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TABLE 2-3: SPARTAN-3 FEATURES AND B
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XILINX SOLUTIONS FIGURE 2-10: SPART
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Delay-Locked Loop XILINX SOLUTIONS
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XILINX SOLUTIONS FIGURE 2-15: SPART
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XILINX SOLUTIONS Low Power - Is you
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XILINX SOLUTIONS XC9500XL family is
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XILINX SOLUTIONS TABLE 2-5: XC9500X
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XILINX SOLUTIONS caded chain of pur
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XILINX SOLUTIONS FIGURE 2-22: COOLR
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I/O Cell XILINX SOLUTIONS The outpu
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TABLE 2-6: VFM (Variable Function M
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XILINX SOLUTIONS Figure 2-27 also d
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XILINX SOLUTIONS At the high level,
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XILINX SOLUTIONS FIGURE 2-30: COOLR
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XILINX SOLUTIONS The larger parts (
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XILINX SOLUTIONS Note that a synchr
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XILINX SOLUTIONS These security bit
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XILINX SOLUTIONS COOLRUNNER REFEREN
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. XILINX SOLUTIONS FIGURE 2-42: LOG
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XILINX SOLUTIONS To address the nee
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XILINX SOLUTIONS This rich mixture
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Dynamic Verification XILINX SOLUTIO
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XILINX SOLUTIONS Xilinx IP Cores Th
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XILINX SOLUTIONS • Test and Measu
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XILINX SOLUTIONS be fixed, upgraded
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XILINX SOLUTIONS TABLE 2-10: XILINX
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XILINX SOLUTIONS CONNECTIVITY CENTR
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XILINX SOLUTIONS design • Broad a
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Xilinx Student Edition Frequently A
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C HAPTER 3 WebPACK ISE Design Softw
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WEBPACK ISE DESIGN SOFTWARE 4. Gene
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WEBPACK ISE DESIGN SOFTWARE WEBPACK
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Summary PROJECTS WEBPACK ISE DESIGN
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C HAPTER 4 WebPACK ISE Design Entry
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WEBPACK ISE DESIGN ENTRY FIGURE 4-2
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WEBPACK ISE DESIGN ENTRY Notice tha
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WEBPACK ISE DESIGN ENTRY As you hav
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WEBPACK ISE DESIGN ENTRY The area s
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Page 127 and 128: WEBPACK ISE DESIGN ENTRY Open the S
Page 129 and 130: WEBPACK ISE DESIGN ENTRY Set RD to
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Page 133 and 134: Click on the Generate HDL button on
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Page 139 and 140: You are now ready to go to the impl
Page 141 and 142: WEBPACK ISE DESIGN ENTRY Move the c
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Page 145 and 146: C HAPTER 5 Implementing CPLDs Intro
Page 147 and 148: IMPLEMENTING CPLDS The design shoul
Page 149 and 150: IMPLEMENTING CPLDS Notice that the
Page 151 and 152: DoubLe-click in the Period window o
Page 153 and 154: IMPLEMENTING CPLDS In the Clock to
Page 155 and 156: IMPLEMENTING CPLDS Click on the “
Page 157 and 158: IMPLEMENTING CPLDS To open the CPLD
Page 159 and 160: IMPLEMENTING CPLDS MXE will open, b
Page 161 and 162: C HAPTER 6 Implementing FPGAs Intro
Page 163 and 164: IMPLEMENTING FPGAS Double-click on
Page 165 and 166: IMPLEMENTING FPGAS The FSM encoding
Page 167 and 168: IMPLEMENTING FPGAS The Constraints
Page 169 and 170: IMPLEMENTING FPGAS Highlight the th
Page 171 and 172: IMPLEMENTING FPGAS Save and close t
Page 173: IMPLEMENTING FPGAS Programming Righ
Page 177 and 178: DESIGN REFERENCE BANK A high-powere
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Page 185 and 186: DESIGN REFERENCE BANK Figure 7-7 sh
Page 187 and 188: DESIGN REFERENCE BANK Full-function
Page 189 and 190: DESIGN REFERENCE BANK TABLE 7-1: DO
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Page 193 and 194: ACRONYMS ABEL ADC AIM ANSI ASIC ASS
Page 195 and 196: ACRONYMS LVDS Low Voltage Different
Page 198 and 199: PROGRAMMABLE LOGIC DESIGN -- QUICK
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