Programmable Logic Design Quick Start Handbook

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PROGRAMMABLE LOGIC DESIGN -- QUICK START HANDBOOK • CHAPTER 6 When synthesis chooses to use primitive macros it is known as “inference.” As registered outputs were selected in the state machine, three further registers were inferred. FIGURE 6-3: EXTRACT OF SYNTHESIS REPORT The Final Report section shows the resources used within the FPGA. FIGURE 6-4: RESOURCE REPORT Xilinx • 152
IMPLEMENTING FPGAS The Constraints File To get the ultimate performance from the device, you must tell the implementation tools what and where performance is required. This design is particularly slow and timing constraints are unnecessary. Constraints can also be physical; pin locking is a physical constraint. For this design, assume that the specification for clock frequency is 100 MHz and that the pin-out has been pre-determined to that of a Spartan-3 device. There are already some constraints in the UCF from the previous project implementation. It will be necessary to delete these constraints. Highlight “top_constraints.ucf” in the Source window. Expand the “+” next to User Constraints and double-click Edit Constraints (Text). Highlight all of the constraints and delete them. Save the UCF and close it. Double-click on Assign Package Pins. Alternatively, you can highlight the top level (“top.vhd”) and expand the User Constraints branch. FIGURE 6-5: PROCESS WINDOW SHOWING ASSIGN PACKAGE PINS The PACE tool will be launched. Assign all I/O pins in the <strong>Design</strong> Object List as follows. reset red_light green_light clock amber_light p36 p44 p52 p55 p46 Xilinx • 153
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Programmable Logic Design Quick Sta
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ABSTRACT Whether you design with di
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NAVIGATING THIS BOOK C HAPTER 5: IM
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TABLE OF CONTENTS Virtex FPGAs.....
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TABLE OF CONTENTS MicroBlaze and Pi
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Chapter 7: Design Reference Bank TA
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C HAPTER 1 Introduction The History
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INTRODUCTION Other architectures fo
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INTRODUCTION vides an instant hardw
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INTRODUCTION FIGURE 1-4: FPGA ARCHI
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INTRODUCTION By using Xilinx CoolRu
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INTRODUCTION FIGURE 1-8: DESIGN SPE
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INTRODUCTION For the HDL specificat
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INTRODUCTION Even if you decide to
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INTRODUCTION original I/O pin place
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INTRODUCTION FIGURE 1-11: DEVICE IM
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C HAPTER 2 Xilinx Solutions Introdu
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XILINX SOLUTIONS The Platform FPGA
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. XILINX SOLUTIONS FIGURE 2-2: PLAT
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XILINX SOLUTIONS FIGURE 2-4: SPARTA
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XILINX SOLUTIONS • Full- and half
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TABLE 2-3: SPARTAN-3 FEATURES AND B
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XILINX SOLUTIONS FIGURE 2-10: SPART
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Delay-Locked Loop XILINX SOLUTIONS
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XILINX SOLUTIONS FIGURE 2-15: SPART
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XILINX SOLUTIONS Low Power - Is you
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XILINX SOLUTIONS XC9500XL family is
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XILINX SOLUTIONS TABLE 2-5: XC9500X
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XILINX SOLUTIONS caded chain of pur
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XILINX SOLUTIONS FIGURE 2-22: COOLR
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I/O Cell XILINX SOLUTIONS The outpu
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TABLE 2-6: VFM (Variable Function M
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XILINX SOLUTIONS Figure 2-27 also d
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XILINX SOLUTIONS At the high level,
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XILINX SOLUTIONS FIGURE 2-30: COOLR
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XILINX SOLUTIONS The larger parts (
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XILINX SOLUTIONS Note that a synchr
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XILINX SOLUTIONS These security bit
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XILINX SOLUTIONS COOLRUNNER REFEREN
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. XILINX SOLUTIONS FIGURE 2-42: LOG
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XILINX SOLUTIONS To address the nee
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XILINX SOLUTIONS This rich mixture
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Dynamic Verification XILINX SOLUTIO
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XILINX SOLUTIONS Xilinx IP Cores Th
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XILINX SOLUTIONS • Test and Measu
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XILINX SOLUTIONS be fixed, upgraded
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XILINX SOLUTIONS TABLE 2-10: XILINX
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XILINX SOLUTIONS CONNECTIVITY CENTR
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XILINX SOLUTIONS design • Broad a
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Xilinx Student Edition Frequently A
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C HAPTER 3 WebPACK ISE Design Softw
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WEBPACK ISE DESIGN SOFTWARE 4. Gene
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WEBPACK ISE DESIGN SOFTWARE WEBPACK
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Summary PROJECTS WEBPACK ISE DESIGN
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C HAPTER 4 WebPACK ISE Design Entry
Page 115 and 116: WEBPACK ISE DESIGN ENTRY FIGURE 4-2
Page 117 and 118: WEBPACK ISE DESIGN ENTRY Notice tha
Page 119 and 120: WEBPACK ISE DESIGN ENTRY As you hav
Page 121 and 122: WEBPACK ISE DESIGN ENTRY The area s
Page 123 and 124: WEBPACK ISE DESIGN ENTRY Click OK t
Page 125 and 126: WEBPACK ISE DESIGN ENTRY Maximize t
Page 127 and 128: WEBPACK ISE DESIGN ENTRY Open the S
Page 129 and 130: WEBPACK ISE DESIGN ENTRY Set RD to
Page 131 and 132: WEBPACK ISE DESIGN ENTRY In the edi
Page 133 and 134: Click on the Generate HDL button on
Page 135 and 136: WEBPACK ISE DESIGN ENTRY Click on t
Page 137 and 138: WEBPACK ISE DESIGN ENTRY Connect th
Page 139 and 140: You are now ready to go to the impl
Page 141 and 142: WEBPACK ISE DESIGN ENTRY Move the c
Page 143 and 144: Your completed schematic should loo
Page 145 and 146: C HAPTER 5 Implementing CPLDs Intro
Page 147 and 148: IMPLEMENTING CPLDS The design shoul
Page 149 and 150: IMPLEMENTING CPLDS Notice that the
Page 151 and 152: DoubLe-click in the Period window o
Page 153 and 154: IMPLEMENTING CPLDS In the Clock to
Page 155 and 156: IMPLEMENTING CPLDS Click on the “
Page 157 and 158: IMPLEMENTING CPLDS To open the CPLD
Page 159 and 160: IMPLEMENTING CPLDS MXE will open, b
Page 161 and 162: C HAPTER 6 Implementing FPGAs Intro
Page 163 and 164: IMPLEMENTING FPGAS Double-click on
Page 165: IMPLEMENTING FPGAS The FSM encoding
Page 169 and 170: IMPLEMENTING FPGAS Highlight the th
Page 171 and 172: IMPLEMENTING FPGAS Save and close t
Page 173 and 174: IMPLEMENTING FPGAS Programming Righ
Page 175 and 176: C HAPTER 7 Design Reference Bank In
Page 177 and 178: DESIGN REFERENCE BANK A high-powere
Page 179 and 180: DESIGN REFERENCE BANK USING A MICRO
Page 181 and 182: DESIGN REFERENCE BANK port ( clk :
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Page 185 and 186: DESIGN REFERENCE BANK Figure 7-7 sh
Page 187 and 188: DESIGN REFERENCE BANK Full-function
Page 189 and 190: DESIGN REFERENCE BANK TABLE 7-1: DO
Page 191 and 192: DESIGN REFERENCE BANK TABLE 7-1: DO
Page 193 and 194: ACRONYMS ABEL ADC AIM ANSI ASIC ASS
Page 195 and 196: ACRONYMS LVDS Low Voltage Different
Page 198 and 199: PROGRAMMABLE LOGIC DESIGN -- QUICK
Page 206: PROGRAMMABLE LOGIC DESIGN -- QUICK
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Programmable Logic Design Quick Start Handbook

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