Programmable Logic Design Quick Start Handbook

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PROGRAMMABLE LOGIC DESIGN -- QUICK START HANDBOOK • CHAPTER 5 Save the Constraints Editor session and exit the Constraints Editor. CoolRunner-II architecture supports the use of non 50:50 duty cycle clocks by implementing input hysteresis. This can be selected on a pin-by-pin basis. For example, if the clock used in this design is an RC oscillator, the input hysteresis can be used to clean up the clock using the following constraint syntax: NET “clock” schmitt_trigger; The CoolRunner-II CPLD also supports different I/O standards. If the three light signals had to go to a downstream device that required the signals to conform to a certain I/O standard, you could use the following constraint syntax: NET “red_light” IOSTANDARD=LVTTL; The permissible standards are LVTTL, LVCMOS15, LVCMOS18, LVCMOS25, LVCMOS33. On larger devices (128 macrocell and larger), the permissible standards are HSTL_I, SSTL2_I, and SSTL3_I. However, you can use only one I/O standard per bank, so take care when assigning different I/O standards in a design. The CoolRunner-II family has several features that are aimed at reducing power consumption in the device. One of these features is known as CoolClock. The clock signal on Global Clock Input 2 (GCK2) is divided by 2 as soon as it enters the device. All of the registers clocked by this clock are then automatically configured as dual-edge triggered flip-flops. The highest toggling net in the design will now be toggling at half the frequency, which will reduce the power consumption of that net without compromising the performance of the design. The CoolClock attribute can be applied by right-clicking on GCK2 in Chip- Viewer or by adding the following line in the UCF: NET “clock” COOL_CLK; However, we will not use these features in this tutorial. For more information on the use of CoolRunner-II CPLDs, and their advanced features, visit www.xilinx.com/apps/epld.htm for a number of application notes, often including free code examples. You must re-run translate so the new constraints can be read. Xilinx • 140
IMPLEMENTING CPLDS Click on the “+” next to Implement <strong>Design</strong> in the Process window. FIGURE 5-10: DESIGN PROCESS WINDOW The implementation steps are now visible. An orange question mark indicates that translate is now out of date and should be re-run. A right-click on Implement <strong>Design</strong> allows you to edit the properties for each particular step. FIGURE 5-11: PROCESS PROPERTIES – IMPLEMENT DESIGN The Help button will explain the operation of each field. You can set the default I/O standard under the Fitting tab of the Process Properties window, as shown in Figure 5-11. Xilinx • 141
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Programmable Logic Design Quick Sta
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ABSTRACT Whether you design with di
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NAVIGATING THIS BOOK C HAPTER 5: IM
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TABLE OF CONTENTS Virtex FPGAs.....
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TABLE OF CONTENTS MicroBlaze and Pi
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Chapter 7: Design Reference Bank TA
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C HAPTER 1 Introduction The History
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INTRODUCTION Other architectures fo
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INTRODUCTION vides an instant hardw
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INTRODUCTION FIGURE 1-4: FPGA ARCHI
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INTRODUCTION By using Xilinx CoolRu
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INTRODUCTION FIGURE 1-8: DESIGN SPE
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INTRODUCTION For the HDL specificat
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INTRODUCTION Even if you decide to
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INTRODUCTION original I/O pin place
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INTRODUCTION FIGURE 1-11: DEVICE IM
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C HAPTER 2 Xilinx Solutions Introdu
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XILINX SOLUTIONS The Platform FPGA
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. XILINX SOLUTIONS FIGURE 2-2: PLAT
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XILINX SOLUTIONS FIGURE 2-4: SPARTA
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XILINX SOLUTIONS • Full- and half
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TABLE 2-3: SPARTAN-3 FEATURES AND B
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XILINX SOLUTIONS FIGURE 2-10: SPART
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Delay-Locked Loop XILINX SOLUTIONS
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XILINX SOLUTIONS FIGURE 2-15: SPART
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XILINX SOLUTIONS Low Power - Is you
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XILINX SOLUTIONS XC9500XL family is
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XILINX SOLUTIONS TABLE 2-5: XC9500X
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XILINX SOLUTIONS caded chain of pur
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XILINX SOLUTIONS FIGURE 2-22: COOLR
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I/O Cell XILINX SOLUTIONS The outpu
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TABLE 2-6: VFM (Variable Function M
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XILINX SOLUTIONS Figure 2-27 also d
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XILINX SOLUTIONS At the high level,
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XILINX SOLUTIONS FIGURE 2-30: COOLR
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XILINX SOLUTIONS The larger parts (
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XILINX SOLUTIONS Note that a synchr
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XILINX SOLUTIONS These security bit
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XILINX SOLUTIONS COOLRUNNER REFEREN
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. XILINX SOLUTIONS FIGURE 2-42: LOG
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XILINX SOLUTIONS To address the nee
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XILINX SOLUTIONS This rich mixture
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Dynamic Verification XILINX SOLUTIO
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XILINX SOLUTIONS Xilinx IP Cores Th
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XILINX SOLUTIONS • Test and Measu
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XILINX SOLUTIONS be fixed, upgraded
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XILINX SOLUTIONS TABLE 2-10: XILINX
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XILINX SOLUTIONS CONNECTIVITY CENTR
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XILINX SOLUTIONS design • Broad a
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Page 105 and 106: C HAPTER 3 WebPACK ISE Design Softw
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Page 109 and 110: WEBPACK ISE DESIGN SOFTWARE WEBPACK
Page 111 and 112: Summary PROJECTS WEBPACK ISE DESIGN
Page 113 and 114: C HAPTER 4 WebPACK ISE Design Entry
Page 115 and 116: WEBPACK ISE DESIGN ENTRY FIGURE 4-2
Page 117 and 118: WEBPACK ISE DESIGN ENTRY Notice tha
Page 119 and 120: WEBPACK ISE DESIGN ENTRY As you hav
Page 121 and 122: WEBPACK ISE DESIGN ENTRY The area s
Page 123 and 124: WEBPACK ISE DESIGN ENTRY Click OK t
Page 125 and 126: WEBPACK ISE DESIGN ENTRY Maximize t
Page 127 and 128: WEBPACK ISE DESIGN ENTRY Open the S
Page 129 and 130: WEBPACK ISE DESIGN ENTRY Set RD to
Page 131 and 132: WEBPACK ISE DESIGN ENTRY In the edi
Page 133 and 134: Click on the Generate HDL button on
Page 135 and 136: WEBPACK ISE DESIGN ENTRY Click on t
Page 137 and 138: WEBPACK ISE DESIGN ENTRY Connect th
Page 139 and 140: You are now ready to go to the impl
Page 141 and 142: WEBPACK ISE DESIGN ENTRY Move the c
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Page 145 and 146: C HAPTER 5 Implementing CPLDs Intro
Page 147 and 148: IMPLEMENTING CPLDS The design shoul
Page 149 and 150: IMPLEMENTING CPLDS Notice that the
Page 151 and 152: DoubLe-click in the Period window o
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Page 157 and 158: IMPLEMENTING CPLDS To open the CPLD
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Page 161 and 162: C HAPTER 6 Implementing FPGAs Intro
Page 163 and 164: IMPLEMENTING FPGAS Double-click on
Page 165 and 166: IMPLEMENTING FPGAS The FSM encoding
Page 167 and 168: IMPLEMENTING FPGAS The Constraints
Page 169 and 170: IMPLEMENTING FPGAS Highlight the th
Page 171 and 172: IMPLEMENTING FPGAS Save and close t
Page 173 and 174: IMPLEMENTING FPGAS Programming Righ
Page 175 and 176: C HAPTER 7 Design Reference Bank In
Page 177 and 178: DESIGN REFERENCE BANK A high-powere
Page 179 and 180: DESIGN REFERENCE BANK USING A MICRO
Page 181 and 182: DESIGN REFERENCE BANK port ( clk :
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Page 185 and 186: DESIGN REFERENCE BANK Figure 7-7 sh
Page 187 and 188: DESIGN REFERENCE BANK Full-function
Page 189 and 190: DESIGN REFERENCE BANK TABLE 7-1: DO
Page 191 and 192: DESIGN REFERENCE BANK TABLE 7-1: DO
Page 193 and 194: ACRONYMS ABEL ADC AIM ANSI ASIC ASS
Page 195 and 196: ACRONYMS LVDS Low Voltage Different
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PROGRAMMABLE LOGIC DESIGN -- QUICK
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PROGRAMMABLE LOGIC DESIGN -- QUICK
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Programmable Logic Design Quick Start Handbook

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