Programmable Logic Design Quick Start Handbook

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PROGRAMMABLE LOGIC DESIGN -- QUICK START HANDBOOK • CHAPTER 5 For this design, assume that the specification for clock frequency is 100 MHz and that the pin-out has been pre-determined to that of a CoolRunner-II pre-designed board. In the Source window, add a New Source of type Implementation Constraints File. Call this file “top_constraints “and associate it with the module “top.” FIGURE 5-2: CONSTRAINTS FILE AS A SOURCE In the Process window, expand the User Constraints section and doubleclick on Assign Package Pins. FIGURE 5-3: ASSIGN PACKAGE PINS IN PACE TOOL Xilinx • 134
IMPLEMENTING CPLDS Notice that the translate step in the Implement Design section runs automatically. This is because the implementation stage must see the netlist before it can offer you the chance to constrain sections of the design. When translate has completed, the Xilinx PACE (Pinout Area and Constraints Editor) tool opens. If there are already constraints in the UCF file, these will be imported by PACE and displayed. As we have an empty UCF file, nothing exists for PACE to import. In the Design Object List, you can enter a variety of constraints on the I/O pins used in the design. PACE recognizes the five pins in the design and displays them in the list. Click in the Loc area next to each signal and enter the following location constraints: clock p38 reset p143 red_light p11 green_light p13 amber_light p12 FIGURE 5-4: ENTER LOCATION CONSTRAINTS When a pin is highlighted in the Design Object List, the pin to which it is “Loc’ed” is highlighted in the Package Pins view. Save the PACE session and exit the PACE tool. It is now possible to see the constraints in the UCF file. With “top_constraints.ucf” highlighted in the Source window, double-click Edit Constraints (Text) in the Process window. The UCF file will open in the main window of the ISE Project Navigator. Xilinx • 135
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Programmable Logic Design Quick Sta
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ABSTRACT Whether you design with di
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NAVIGATING THIS BOOK C HAPTER 5: IM
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TABLE OF CONTENTS Virtex FPGAs.....
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TABLE OF CONTENTS MicroBlaze and Pi
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Chapter 7: Design Reference Bank TA
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C HAPTER 1 Introduction The History
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INTRODUCTION Other architectures fo
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INTRODUCTION vides an instant hardw
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INTRODUCTION FIGURE 1-4: FPGA ARCHI
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INTRODUCTION By using Xilinx CoolRu
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INTRODUCTION FIGURE 1-8: DESIGN SPE
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INTRODUCTION For the HDL specificat
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INTRODUCTION Even if you decide to
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INTRODUCTION original I/O pin place
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INTRODUCTION FIGURE 1-11: DEVICE IM
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C HAPTER 2 Xilinx Solutions Introdu
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XILINX SOLUTIONS The Platform FPGA
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. XILINX SOLUTIONS FIGURE 2-2: PLAT
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XILINX SOLUTIONS FIGURE 2-4: SPARTA
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XILINX SOLUTIONS • Full- and half
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TABLE 2-3: SPARTAN-3 FEATURES AND B
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XILINX SOLUTIONS FIGURE 2-10: SPART
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Delay-Locked Loop XILINX SOLUTIONS
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XILINX SOLUTIONS FIGURE 2-15: SPART
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XILINX SOLUTIONS Low Power - Is you
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XILINX SOLUTIONS XC9500XL family is
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XILINX SOLUTIONS TABLE 2-5: XC9500X
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XILINX SOLUTIONS caded chain of pur
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XILINX SOLUTIONS FIGURE 2-22: COOLR
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I/O Cell XILINX SOLUTIONS The outpu
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TABLE 2-6: VFM (Variable Function M
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XILINX SOLUTIONS Figure 2-27 also d
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XILINX SOLUTIONS At the high level,
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XILINX SOLUTIONS FIGURE 2-30: COOLR
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XILINX SOLUTIONS The larger parts (
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XILINX SOLUTIONS Note that a synchr
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XILINX SOLUTIONS These security bit
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XILINX SOLUTIONS COOLRUNNER REFEREN
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. XILINX SOLUTIONS FIGURE 2-42: LOG
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XILINX SOLUTIONS To address the nee
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XILINX SOLUTIONS This rich mixture
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Dynamic Verification XILINX SOLUTIO
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XILINX SOLUTIONS Xilinx IP Cores Th
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XILINX SOLUTIONS • Test and Measu
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XILINX SOLUTIONS be fixed, upgraded
Page 97 and 98: XILINX SOLUTIONS TABLE 2-10: XILINX
Page 99 and 100: XILINX SOLUTIONS CONNECTIVITY CENTR
Page 101 and 102: XILINX SOLUTIONS design • Broad a
Page 103 and 104: Xilinx Student Edition Frequently A
Page 105 and 106: C HAPTER 3 WebPACK ISE Design Softw
Page 107 and 108: WEBPACK ISE DESIGN SOFTWARE 4. Gene
Page 109 and 110: WEBPACK ISE DESIGN SOFTWARE WEBPACK
Page 111 and 112: Summary PROJECTS WEBPACK ISE DESIGN
Page 113 and 114: C HAPTER 4 WebPACK ISE Design Entry
Page 115 and 116: WEBPACK ISE DESIGN ENTRY FIGURE 4-2
Page 117 and 118: WEBPACK ISE DESIGN ENTRY Notice tha
Page 119 and 120: WEBPACK ISE DESIGN ENTRY As you hav
Page 121 and 122: WEBPACK ISE DESIGN ENTRY The area s
Page 123 and 124: WEBPACK ISE DESIGN ENTRY Click OK t
Page 125 and 126: WEBPACK ISE DESIGN ENTRY Maximize t
Page 127 and 128: WEBPACK ISE DESIGN ENTRY Open the S
Page 129 and 130: WEBPACK ISE DESIGN ENTRY Set RD to
Page 131 and 132: WEBPACK ISE DESIGN ENTRY In the edi
Page 133 and 134: Click on the Generate HDL button on
Page 135 and 136: WEBPACK ISE DESIGN ENTRY Click on t
Page 137 and 138: WEBPACK ISE DESIGN ENTRY Connect th
Page 139 and 140: You are now ready to go to the impl
Page 141 and 142: WEBPACK ISE DESIGN ENTRY Move the c
Page 143 and 144: Your completed schematic should loo
Page 145 and 146: C HAPTER 5 Implementing CPLDs Intro
Page 147: IMPLEMENTING CPLDS The design shoul
Page 151 and 152: DoubLe-click in the Period window o
Page 153 and 154: IMPLEMENTING CPLDS In the Clock to
Page 155 and 156: IMPLEMENTING CPLDS Click on the “
Page 157 and 158: IMPLEMENTING CPLDS To open the CPLD
Page 159 and 160: IMPLEMENTING CPLDS MXE will open, b
Page 161 and 162: C HAPTER 6 Implementing FPGAs Intro
Page 163 and 164: IMPLEMENTING FPGAS Double-click on
Page 165 and 166: IMPLEMENTING FPGAS The FSM encoding
Page 167 and 168: IMPLEMENTING FPGAS The Constraints
Page 169 and 170: IMPLEMENTING FPGAS Highlight the th
Page 171 and 172: IMPLEMENTING FPGAS Save and close t
Page 173 and 174: IMPLEMENTING FPGAS Programming Righ
Page 175 and 176: C HAPTER 7 Design Reference Bank In
Page 177 and 178: DESIGN REFERENCE BANK A high-powere
Page 179 and 180: DESIGN REFERENCE BANK USING A MICRO
Page 181 and 182: DESIGN REFERENCE BANK port ( clk :
Page 183 and 184: DESIGN REFERENCE BANK vated, it wil
Page 185 and 186: DESIGN REFERENCE BANK Figure 7-7 sh
Page 187 and 188: DESIGN REFERENCE BANK Full-function
Page 189 and 190: DESIGN REFERENCE BANK TABLE 7-1: DO
Page 191 and 192: DESIGN REFERENCE BANK TABLE 7-1: DO
Page 193 and 194: ACRONYMS ABEL ADC AIM ANSI ASIC ASS
Page 195 and 196: ACRONYMS LVDS Low Voltage Different
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PROGRAMMABLE LOGIC DESIGN -- QUICK
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Programmable Logic Design Quick Start Handbook

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