Programmable Logic Design Quick Start Handbook

WEBPACK ISE DESIGN ENTRY
Connect the counter and state machine instantiated modules so that your
“top.vhd” file looks like Figure 4-29.
FIGURE 4-29: TOP.VHD FILE
When you save “top.vhd,” notice how the Sources window automatically
manages the hierarchy of the whole design, with “counter.vhd” and
“stat_mac.vhd” becoming sub-modules of “top.vhd.”
You can now simulate the entire design.
Add a new testbench waveform source as before, but this time, associate it
with the module “top.”
Accept the timing in the Initialize Timing dialog box and click OK.
In the waveform diagram, enter the input stimulus as follows:
Set the RESET cell below CLK cycle 1 to a value of “1.”
Xilinx • 123