Programmable Logic Design Quick Start Handbook

PROGRAMMABLE LOGIC DESIGN -- QUICK START HANDBOOK • CHAPTER 4
Top-Level VHDL Designs
At this point in the flow, two modules in the design are connected together
by a top-level file.
Some designers like to create a top-level schematic diagram, while others
like to keep the design entirely text-based.
Because this section discusses the latter, the counter and state machine will
be connected using a top.vhd file.
If you prefer the former, jump directly to the next section Top-Level Schematic
Designs, page 125. You will have the opportunity to do both by continuing
through this tutorial.
Take a snapshot of the project from Project > Take Snapshot.
FIGURE 4-24:
PROJECT SNAPSHOT
From the Project menu, select New Source and create a VHDL module
called “top.”
FIGURE 4-25:
NEW SOURCE WINDOW SHOWING VHDL MODULE
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