Programmable Logic Design Quick Start Handbook

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PROGRAMMABLE LOGIC DESIGN -- QUICK START HANDBOOK • CHAPTER 3 The flow diagram below shows the similarities and differences between CPLD and FPGA software flows. FIGURE 3-1: WEBPACK SOFTWARE DESIGN FLOW When your design is complete and you’re happy with the simulation results, you can then download the design to the required device. Although we’ll discuss details of the software flow in Chapters 5 and 6, here’s a basic overview. For FPGAs, the implementation process includes four key steps. 1. Translate – Interprets the design and runs a “design rule check.” 2. Map – Calculates and allocates resources in the targeted device. 3. Place and Route – Places the CLBs in a logical position and utilizes the routing resources. Xilinx • 92
WEBPACK ISE DESIGN SOFTWARE 4. Generate Programming File – Creates a programming bitstream. For CPLDs, the implementation process includes: 1. Translate – Interprets the design and runs a “design rule check.” 2. Fit – Allocates resource usage and connections. 3. Generate Programming File – Creates a JED file for programming. WebPACK <strong>Design</strong> Suite TABLE 3-1: WEBPACK DEVICE SUPPORT Device Support Virtex-II Pro Virtex-II Virtex-E Spartan-IIE Spartan-II Spartan-3 CoolRunner-II CoolRunner XC9500 Families Up to XC2VP2 Up to XC2V250 Up to XCV300E Up to XC2S300E Up to XC2S200 Up to XC3S400 All All All WEBPACK DESIGN ENTRY The WebPACK tool suite supports several different design entries. The XST synthesis tool synthesizes HDL code in VHDL, Verilog, or ABEL into a netlist. Schematic designs are converted into VHDL or Verilog, which are then synthesized by XST in the same way. WEBPACK STATECAD StateCAD is a tool for graphically entering state machines in “bubble diagram” form. You simply draw the states, transitions, and outputs, and StateCAD gives a visual test facility. State machines are generated in HDL and then added to the WebPACK ISE project. Xilinx • 93
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Programmable Logic Design Quick Sta
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ABSTRACT Whether you design with di
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NAVIGATING THIS BOOK C HAPTER 5: IM
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TABLE OF CONTENTS Virtex FPGAs.....
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TABLE OF CONTENTS MicroBlaze and Pi
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Chapter 7: Design Reference Bank TA
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C HAPTER 1 Introduction The History
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INTRODUCTION Other architectures fo
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INTRODUCTION vides an instant hardw
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INTRODUCTION FIGURE 1-4: FPGA ARCHI
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INTRODUCTION By using Xilinx CoolRu
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INTRODUCTION FIGURE 1-8: DESIGN SPE
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INTRODUCTION For the HDL specificat
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INTRODUCTION Even if you decide to
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INTRODUCTION original I/O pin place
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INTRODUCTION FIGURE 1-11: DEVICE IM
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C HAPTER 2 Xilinx Solutions Introdu
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XILINX SOLUTIONS The Platform FPGA
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. XILINX SOLUTIONS FIGURE 2-2: PLAT
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XILINX SOLUTIONS FIGURE 2-4: SPARTA
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XILINX SOLUTIONS • Full- and half
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TABLE 2-3: SPARTAN-3 FEATURES AND B
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XILINX SOLUTIONS FIGURE 2-10: SPART
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Delay-Locked Loop XILINX SOLUTIONS
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XILINX SOLUTIONS FIGURE 2-15: SPART
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Page 59 and 60: XILINX SOLUTIONS TABLE 2-5: XC9500X
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Page 69 and 70: XILINX SOLUTIONS Figure 2-27 also d
Page 71 and 72: XILINX SOLUTIONS At the high level,
Page 73 and 74: XILINX SOLUTIONS FIGURE 2-30: COOLR
Page 75 and 76: XILINX SOLUTIONS The larger parts (
Page 77 and 78: XILINX SOLUTIONS Note that a synchr
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Page 81 and 82: XILINX SOLUTIONS COOLRUNNER REFEREN
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Page 85 and 86: XILINX SOLUTIONS To address the nee
Page 87 and 88: XILINX SOLUTIONS This rich mixture
Page 89 and 90: Dynamic Verification XILINX SOLUTIO
Page 91 and 92: XILINX SOLUTIONS Xilinx IP Cores Th
Page 93 and 94: XILINX SOLUTIONS • Test and Measu
Page 95 and 96: XILINX SOLUTIONS be fixed, upgraded
Page 97 and 98: XILINX SOLUTIONS TABLE 2-10: XILINX
Page 99 and 100: XILINX SOLUTIONS CONNECTIVITY CENTR
Page 101 and 102: XILINX SOLUTIONS design • Broad a
Page 103 and 104: Xilinx Student Edition Frequently A
Page 105: C HAPTER 3 WebPACK ISE Design Softw
Page 109 and 110: WEBPACK ISE DESIGN SOFTWARE WEBPACK
Page 111 and 112: Summary PROJECTS WEBPACK ISE DESIGN
Page 113 and 114: C HAPTER 4 WebPACK ISE Design Entry
Page 115 and 116: WEBPACK ISE DESIGN ENTRY FIGURE 4-2
Page 117 and 118: WEBPACK ISE DESIGN ENTRY Notice tha
Page 119 and 120: WEBPACK ISE DESIGN ENTRY As you hav
Page 121 and 122: WEBPACK ISE DESIGN ENTRY The area s
Page 123 and 124: WEBPACK ISE DESIGN ENTRY Click OK t
Page 125 and 126: WEBPACK ISE DESIGN ENTRY Maximize t
Page 127 and 128: WEBPACK ISE DESIGN ENTRY Open the S
Page 129 and 130: WEBPACK ISE DESIGN ENTRY Set RD to
Page 131 and 132: WEBPACK ISE DESIGN ENTRY In the edi
Page 133 and 134: Click on the Generate HDL button on
Page 135 and 136: WEBPACK ISE DESIGN ENTRY Click on t
Page 137 and 138: WEBPACK ISE DESIGN ENTRY Connect th
Page 139 and 140: You are now ready to go to the impl
Page 141 and 142: WEBPACK ISE DESIGN ENTRY Move the c
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Page 145 and 146: C HAPTER 5 Implementing CPLDs Intro
Page 147 and 148: IMPLEMENTING CPLDS The design shoul
Page 149 and 150: IMPLEMENTING CPLDS Notice that the
Page 151 and 152: DoubLe-click in the Period window o
Page 153 and 154: IMPLEMENTING CPLDS In the Clock to
Page 155 and 156: IMPLEMENTING CPLDS Click on the “
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IMPLEMENTING CPLDS To open the CPLD
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IMPLEMENTING CPLDS MXE will open, b
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C HAPTER 6 Implementing FPGAs Intro
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IMPLEMENTING FPGAS Double-click on
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IMPLEMENTING FPGAS The FSM encoding
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IMPLEMENTING FPGAS The Constraints
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IMPLEMENTING FPGAS Highlight the th
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IMPLEMENTING FPGAS Save and close t
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IMPLEMENTING FPGAS Programming Righ
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C HAPTER 7 Design Reference Bank In
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DESIGN REFERENCE BANK A high-powere
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DESIGN REFERENCE BANK USING A MICRO
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DESIGN REFERENCE BANK port ( clk :
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DESIGN REFERENCE BANK vated, it wil
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DESIGN REFERENCE BANK Figure 7-7 sh
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DESIGN REFERENCE BANK Full-function
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DESIGN REFERENCE BANK TABLE 7-1: DO
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DESIGN REFERENCE BANK TABLE 7-1: DO
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ACRONYMS ABEL ADC AIM ANSI ASIC ASS
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ACRONYMS LVDS Low Voltage Different
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PROGRAMMABLE LOGIC DESIGN -- QUICK
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Programmable Logic Design Quick Start Handbook

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