Programmable Logic Design Quick Start Handbook
Programmable Logic Design Quick Start Handbook
Programmable Logic Design Quick Start Handbook
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PROGRAMMABLE LOGIC DESIGN: QUICK START HANDBOOK •<br />
WebPACK iMPACT Programmer .......................................................... 94<br />
WebPACK ChipViewer............................................................................ 95<br />
XPower........................................................................................................ 95<br />
WebPACK CD-ROM Installation...................................................................... 95<br />
Getting <strong>Start</strong>ed..................................................................................................... 96<br />
Licenses....................................................................................................... 96<br />
Projects ........................................................................................................ 97<br />
Summary .............................................................................................................. 97<br />
Xilinx • x<br />
Chapter 4: WebPACK ISE<br />
<strong>Design</strong> Entry<br />
Introduction.......................................................................................................... 99<br />
<strong>Design</strong> Entry....................................................................................................... 100<br />
The Language Template......................................................................... 104<br />
Close the Language Templates.............................................................. 104<br />
Edit the Counter Module........................................................................ 105<br />
Save the Counter Module....................................................................... 107<br />
Functional Simulation....................................................................................... 107<br />
State Machine Editor......................................................................................... 112<br />
Top-Level VHDL <strong>Design</strong>s................................................................................ 120<br />
Top-Level Schematic <strong>Design</strong>s.......................................................................... 125<br />
ECS Hints.................................................................................................. 125<br />
I/O Markers ............................................................................................. 128<br />
Chapter 5: Implementing CPLDs<br />
Introduction........................................................................................................ 131<br />
Synthesis ............................................................................................................. 132<br />
Constraints Editor ............................................................................................. 133<br />
CPLD Reports .................................................................................................... 142<br />
Timing Simulation............................................................................................. 144<br />
Configuration..................................................................................................... 145<br />
Chapter 6: Implementing FPGAs<br />
Introduction........................................................................................................ 147<br />
Synthesis ............................................................................................................. 150<br />
The Constraints File .......................................................................................... 153<br />
FPGA Reports .................................................................................................... 158<br />
Programming ..................................................................................................... 159<br />
Summary ............................................................................................................ 159