QDK PIC24/dsPIC-XC16 - Quantum Leaps

QDK
PIC24/dsPIC-XC16
www.state-machine.com/pic
1.4 About the QP Port to PIC24/dsPIC
Figure 4 shows the architecture of the QP port to PIC24/dsPIC. The port takes advantage of the
PIC24/dsPIC interrupt priority level (IPL) management hardware. In both cooperative and preemptive QP
ports the hardware priority levels are allocated as follows:
1. All QP tasks (active objects) as well as the QP idle loop execute at the lowest IPL of zero.
2. IPL levels 1 through 6 are used for maskable interrupts. These maskable interrupts (IPL 1..6) can call
QP services, such as QF_tick(), QActive_postFIFO(), QF_publish(), and Q_NEW(). The
maskable interrupts can nest on each other, which is the default in PIC24/dsPIC.
3. This QP port never disables the IPL level 7, which is the Non-Maskable Interrupt (NMI) level. The
NMI-level interrupt(s) cannot call any QP services. But the NMI can trigger a maskable interrupt, as
shown by the dashed arrow in Figure 4. This triggered interrupt of IPL 1..6 can call QP services for
signaling the QP tasks (active objects).
Figure 4: Architecture of the PIC24/dsPIC port
(IPL = 7) Non-Maskable Interrupt (NMI)
IPL Level 7
(NMI level)
(IPL = 6) User interrupt
(IPL = 5) User interrupt
(IPL = 4) User interrupt
IPL Levels 1-6
(interrupt level)
(IPL = 3) User interrupt
(IPL = 2) User interrupt
(IPL = 1) User interrupt
(QP prio = n) User task (active object)
(QP prio = n-1) User task (active object)
. . .
(QP prio = 2) User task (active object)
IPL Level 0
(task level)
(QP prio = 1) User task (active object)
(QP prio = 0) Idle task
This layered software architecture fits very naturally with the PIC24/dsPIC hardware. The QP ports (both
cooperative and preemptive) allow nesting of interrupts, which is the default in PIC24/dsPIC. Both
cooperative and preemptive QP ports can work with the interrupt service routines (ISRs) generated by the
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