QDK PIC24/dsPIC-XC16 - Quantum Leaps

QDK
PIC24/dsPIC-XC16
www.state-machine.com/pic
void QK_onIdle(void) {
Listing 10: QK_onIdle() callback for PIC24/dsPIC.
#ifdef Q_SPY
while (U2STAbits.UTXBF == 0U) { /* TX Buffer not full */
uint16_t b;
QF_INT_DISABLE();
b = QS_getByte();
QF_INT_ENABLE();
if (b == QS_EOD) { /* End-Of-Data reached */
break; /* break out of the loop */
}
U2TXREG = (uint8_t)b; /* stick the byte to TXREG for transmission */
}
#elif defined NDEBUG
Idle(); /* transition to Idle mode */
#endif
}
4.4 Testing QK Preemption Scenarios
The technique described in this section will allow you to use the MPLAB debugger to trigger an interrupt
at any machine instruction and observe the preemptions it causes. The interrupt used for the testing
purposes is the GPIOA interrupt (INTID == 0). The ISR for this interrupt is shown below:
The DPP example application for the preemptive QK kernel includes special ISR (INT0 ISR) for
convenient testing of various preemption scenarios, defined as follows:
#define INT0_ISR_PRIO 6
QK_ISR(auto_psv) _INT0Interrupt() {
static QEvt const eat_evt = { EAT_SIG, 0U, 0U };
_INT0IF = 0;
QACTIVE_POST(AO_Table, &eat_evt, &l_INT0Interrupt);
QK_ISR_EXIT(); /* inform QK about exiting the ISR */
}
The INT0 ISR, is assigned priority 6, which is higher than the priority of the system clock tick ISR.
Figure 10 shows how to trigger the INT0 interrupt from the MPLABX debugger. From the debugger you
need to first open the “File Registers” window (menu View | File Registers) as shown in Figure 10. You
scroll to the IFS0 register at address 0x0084. To trigger the INT0 interrupt you need to write 1 to the leastsignificant
bit (bit #0) of the IFS0 register.
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