QDK PIC24/dsPIC-XC16 - Quantum Leaps

QDK
PIC24/dsPIC-XC16
www.state-machine.com/pic
3.3.1 PSV Usage in ISRs
This QP port to PIC24/dsPIC can work with ISRs that preserve the PSVPAG register as well as ISRs that
don’t. The preserving of the PSVPAG register is controlled by the attributes auto_psv and no_auto_psv
that the XC16 compiler supports for this purpose (see Listing 4(2)).
If an ISR references const variables or string literals using the constants-in-code memory model, the
auto_psv attribute should be added to the ISR definition. This attribute will cause the compiler to
preserve the previous contents of PSVPAG and set it to section .const. Upon exit, the previous value of
PSVPAG will be restored. Alternatively, if the ISR does not access the PSVPAG access, the attribute
no_auto_psv can be used (see Section 8.10 in [XC16] for more details). The no_auto_psv attribute
results in slightly faster ISR with one register less saved on the stack.
3.3.2 Shadow Registers Usage in ISRs
The non-preemptive “vanilla” QP port to PIC24/dsPIC can work with ISRs that preserve the context in the
shadow registers available in the PIC24/dsPIC CPU. To request the compiler to use the fast context save
(using the push.s and pop.s instructions), tag the function with the __shadow__ attribute. For example:
void __attribute__((__interrupt__, __shadow__)) _T2Interrupt(void);
NOTE: Generally, shadow registers should be used at one IPL level only (typically the highest).
When interrupt nesting is allowed, which is the default in the PIC24/dsPIC architecture, the shadow
registers can get corrupted if they are used by interrupts of two or more different IPL levels.
3.3.3 Assigning/Changing Interrupt Priorities in Software
Each ISR in PIC24/dsPIC runs at a pre-configured IPL level. The default IPL level assigned to all ISRs out
of reset is 4. It is strongly recommended, however, to assign priority to each used interrupt explicitly
before enabling the interrupt. For example, the highlighted code in Listing 5 shows assigning the priority
to the Timer2 interrupt in function QF_onStartup():
Listing 5: Configuring interrupts in function QF_onStartup() (file bsp.c)
#define TIMER2_ISR_PRIO 4
. . .
void QF_onStartup(void) { /* entered with interrupts locked */
T2CON = 0; /* Use Internal Osc (Fcy), 16 bit mode, prescaler = 1 */
TMR2 = 0; /* Start counting from 0 and clear the prescaler count */
PR2 = (uint16_t)(BSP_TMR2_PERIOD – 1.0 + 0.5); /* Timer2 period */
_T2IP = TIMER2_ISR_PRIO; /* set Timer 2 interrupt priority */
_T2IF = 0; /* clear the interrupt for Timer 2 */
_T2IE = 1; /* enable interrupt for Timer 2 */
T2CONbits.TON = 1; /* start Timer 2 */
}
3.4 QP Idle Loop Customization in QF_onIdle()
The cooperative “vanilla” kernel can very easily detect the situation when no events are available, in
which case QF_run() calls the QF_onIdle() callback. You can use QF_onIdle() to suspended the CPU
to save power, if your CPU supports such a power-saving mode. Please note that QF_onIdle() is called
repetitively from the event loop whenever the event loop has no more events to process, in which case
only an interrupt can provide new events. The QF_onIdle() callback is called with interrupts locked,
because the determination of the idle condition might change by any interrupt posting an event.
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