QDK PIC24/dsPIC-XC16 - Quantum Leaps

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QDK PIC24/dsPIC-XC16 www.state-machine.com/pic 3 Cooperative “Vanilla” Port The “vanilla” port shows how to use QP on a bare metal PIC24-dsPIC-based system with the cooperative “vanilla” kernel. In this version you’re using the non-preemptive kernel built-into the QF framework and your’e not using the QK component. 3.1 The qep_port.h Header File The QEP header file for the PIC24/dsPIC port is located in \ports\pic24- dspic\vanilla\xc16\qep_port.h. Listing 2 shows the qep_port.h header file for PIC24/dsPIC. NOTE: The QP port to the cooperative “Vanilla” kernel qep_port.h is generic and should not need to change for other PIC24/dsPIC applications. Listing 2: qep_port.h header file for the cooperative QP configuration and XC16 compiler #ifndef qep_port_h #define qep_port_h /* Exact-width types. WG14/N843 C99 Standard, Section 7.18.1.1 */ (1) #include #include "qep.h" /* QEP platform-independent public interface */ #endif /* qep_port_h */ (1) The XC16 compiler support the C99 exact-width integer types the standard header file. 3.2 The qf_port.h Header File The QF header file for the PIC24/dsPIC port is located in \ports\pic24-dspic\ vanilla\xc16\qf_port.h. This file specifies the interrupt locking/unlocking policy (QF critical section) as well as the configuration constants for QF (see Chapter 8 in [PSiCC2]). The most important porting decision you need to make in the qf_port.h header file is the policy for locking and unlocking interrupts. The PIC24/dsPIC CPU allows using the simplest “unconditional interrupt unlocking” policy (see Section 7.3.2 of the book “Practical UML Statecharts in C/C++, Second Edition” [PSiCC2]), because PIC24/dsPIC can mask interrupt groups (INT1 - INT12) and individual interrupts in the Peripheral Interrupt Expansion (PIE) module. Listing 3 shows the qf_port.h header file for PIC24/dsPIC. Listing 3: The qf_port.h header file for PIC24/dsPIC. /* The maximum number of active objects in the application, see NOTE01 */ (1) #define QF_MAX_ACTIVE 8 (2) #define QF_EVENT_SIZ_SIZE 1 (3) #define QF_EQUEUE_CTR_SIZE 1 (4) #define QF_MPOOL_SIZ_SIZE 1 (5) #define QF_MPOOL_CTR_SIZE 1 Copyright © Quantum Leaps, LLC. All Rights Reserved. 12 of 35
QDK PIC24/dsPIC-XC16 www.state-machine.com/pic (6) #define QF_TIMEEVT_CTR_SIZE 2 /* QF interrupt disable/enable, see NOTE02 */ (7) #define QF_INT_DISABLE() __builtin_disi(0x3FFFU) (8) #define QF_INT_ENABLE() __builtin_disi(0x0000U) /* QF critical section entry/exit, see NOTE02 */ (9) /* QF_CRIT_STAT_TYPE not defined: unconditional interrupt unlocking" policy */ (10) #define QF_CRIT_ENTRY(dummy) __builtin_disi(0x3FFFU) (11) #define QF_CRIT_EXIT(dummy) __builtin_disi(0x0000U) /* fast log-base-2 with FBCL instruction, NOTE03 */ (12) #define QF_LOG2(n_) ((uint8_t)(15 + __builtin_fbcl(n_))) #include "qep_port.h" /* QEP port */ #include "qvanilla.h" /* "Vanilla" cooperative kernel */ #include "qf.h" /* QF platform-independent public interface */ (1) The QF_MAX_ACTIVE specifies the maximum number of active object priorities in the application. You always need to provide this constant in the QF port. Here, QF_MAX_ACTIVE is set to 8 to conserve some RAM, but you can increase this value up to 63 inclusive. (2-5) These object sizes in QF are all set to 1, meaning that uint8_t will be used to represent the various object sizes. NOTE: Please refer to Chapter 8 of [PSiCC2] for discussion of all configurable QF parameters. (6) These time event counter is configured to 2-bytes, meaning that timeouts of up to 65535 clock ticks can be handled in this QF port. (7) The interrupt disable macro resolves to the single instruction DISI #0x3FFF, which disables interrupts for 16383 instruction cycles. The number of cycles is much longer than any actual critical section in QP. NOTE: The DISI instruction only disables interrupts with priority levels 1-6. Priority level 7 interrupts and all trap events still have the ability to interrupt the CPU when the DISI instruction is active. This means that from the perspective of QP, the level 7 interrupts are treated as non-maskable interrupts (NMIs). Such non-maskable interrupts cannot call any QP services. In particular, they cannot post events (see also Section 5). (8) The DISI #0 instruction is then used to unconditionally unlock the interrupts at the end of the critical section. (9) The QF_CRIT_STAT_TYPE macro is not defined, which means that the simple policy of “unconditional interrupt disabling and enabling” is applied (see Section 7.3 in [PSiCC2]). (10) The critical section entry macro disables interrupts (see step (7)). (11) The critical section exit macro unconditionally enables interrupts (see step (8)). (12) The QF_LOG2() macro is defined to take advantage of the FBCL instruction. NOTE: FBCL instruction (Find First Bit Change Left) determines the exponent of a value by detecting the first bit change starting from the value’s sign bit and working towards the LSB. Since the PIC24/dsPIC’s barrel shifter uses negative values to specify a left shift, the FBCL instruction returns the negated exponent of a value. This value added to 15 gives the log-2. Copyright © Quantum Leaps, LLC. All Rights Reserved. 13 of 35
Page 1 and 2: QP state machine frameworks for PIC
Page 3 and 4: 1 Introduction This QP Development
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QDK PIC24/dsPIC-XC16 - Quantum Leaps

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