Tutorial Xilinx Virtex-5 FPGA ML506 Edition

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WriteAC97Reg(AC97_ExtendedAudioStat,1); // Enabling VRA mode WriteAC97Reg(AC97_PCM_DAC_Rate1, 48000); // sampling rate PLAY WriteAC97Reg(AC97_PCM_DAC_Rate0, 48000); // sampling rate rec xil_printf ("DAC sample rate= %d hz\n\r", ReadAC97Reg (AC97_PCM_DAC_Rate1)); xil_printf ("ADC sample rate= %d hz\n\r", ReadAC97Reg (AC97_PCM_DAC_Rate0)); xil_printf ("vendor id 1= %x\n\r", ReadAC97Reg (AC97_VendorID1)); xil_printf ("vendor id 2= %x\n\r", ReadAC97Reg (AC97_VendorID2)); // Turn back on power to ADC and DAC WriteAC97Reg(AC97_PowerDown,0x0000); usleep (100000); xil_printf ("PowerDown Reg State (Should be 0x000F) = %x \n\r", ReadAC97Reg (AC97_PowerDown)); xil_printf ("Misc Control Bits = %x\n\r", ReadAC97Reg (AC97_MiscControlBits)); XIo_Out32(AC97_Control, 0x00000003); // clear FIFOs XIo_Out32(AC97_InFIFO, 0); XIo_Out32(AC97_InFIFO, 0); XIo_Out32(AC97_InFIFO, 0); XIo_Out32(AC97_InFIFO, 0); XIo_Out32(AC97_InFIFO, 0); XIo_Out32(AC97_InFIFO, 0); XIo_Out32(AC97_InFIFO, 0); XIo_Out32(AC97_InFIFO, 0); XIo_Out32(AC97_InFIFO, 0); XIo_Out32(AC97_InFIFO, 0); XIo_Out32(AC97_InFIFO, 0); XIo_Out32(AC97_InFIFO, 0); XIo_Out32(AC97_InFIFO, 0); XIo_Out32(AC97_InFIFO, 0); XIo_Out32(AC97_InFIFO, 0); XIo_Out32(AC97_InFIFO, 0); // turn off digital loopback WriteAC97Reg(AC97_GeneralPurpose,0x0000); xil_printf ("General Purpose reg state = %x\n\r", ReadAC97Reg (AC97_GeneralPurpose)); WriteAC97Reg(AC97_SerialConfig,0x7000); xil_printf ("config reg state = %x\n\r", ReadAC97Reg (AC97_SerialConfig)); WriteAC97Reg(AC97_MasterVol, AC97_VolMid); WriteAC97Reg(AC97_HeadphoneVol, AC97_VolMid); WriteAC97Reg(AC97_MasterVolMono, AC97_VolMid); WriteAC97Reg(AC97_PCBeepVol, AC97_VolMute); WriteAC97Reg(AC97_PhoneInVol, AC97_VolMute); WriteAC97Reg(AC97_CDVol, AC97_VolMute); WriteAC97Reg(AC97_VideoVol, AC97_VolMute); WriteAC97Reg(AC97_AuxVol, AC97_VolMute); WriteAC97Reg(AC97_PCMOutVol, AC97_VolMid); WriteAC97Reg(AC97_RecordSelect, 0x0000); 98
WriteAC97Reg(AC97_MicVol, WriteAC97Reg(AC97_LineInVol, } 0x0040); AC97_VolMid); void play_sound(){ int i; int j; xil_printf ("Play Start\n\r"); sound_ptr = DDR_BASEADDR; WriteAC97Reg(AC97_RecordGain, AC97_VolMute); WriteAC97Reg(AC97_PowerDown, 0x0100); WriteAC97Reg(AC97_LineInVol, AC97_VolMute); i = 0; do { XIo_Out32(AC97_Control, 0x00000003); // clear FIFOs XIo_Out32(AC97_InFIFO, 0); XIo_Out32(AC97_InFIFO, 0); XIo_Out32(AC97_InFIFO, 0); XIo_Out32(AC97_InFIFO, 0); XIo_Out32(AC97_InFIFO, 0); XIo_Out32(AC97_InFIFO, 0); XIo_Out32(AC97_InFIFO, 0); XIo_Out32(AC97_InFIFO, 0); } while (XIo_In32(AC97_FIFO_Status) & 0x0040); while (1) { if (XIo_In32(AC97_FIFO_Status) & 0x0040) xil_printf ("play underrun\n\r"); while (XIo_In32(AC97_FIFO_Status) & AC97_InFIFO_Half_Full) {}; // The frequency is 44.1kHz so if we divide 44.1kHz by 22 we // get 2004.54 ~ 2kHz sine wave switch ((i) % freq) { case 0: j = 0 ; break; case 1: j = 9232; break; case 2: j = 17715; break; case 3: j = 24764; break; case 4: j = 29806; break; case 5: j = 32434; break; case 6: j = 32435; break; case 7: j = 29808; break; case 8: j = 24766; break; case 9: j = 17718; break; case 10: j = 9234; break; case 11: j = 3; break; case 12: j = -9229; break; case 13: j = -17713; break; case 14: j = -24762; break; case 15: j = -29805; break; case 16: j = -32434; break; case 17: j = -32435; break; case 18: j = -29809; break; case 19: j = -24768; break; case 20: j = -17720; break; case 21: j = -9237; break; } i = i+1; 99
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Tutorial Xilinx Virtex-5 FPGA ML506
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Blank Page 3
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Setting up the ML506 board The ML50
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• Set SW6 (on the back side of th
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• Go to setup → serial port, an
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Illustration 1: SACE ERR, CF card i
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Once this is complete, right-click
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After connecting your board. Run Te
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The VHDL Design Open up Xilinx ISE.
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Now setup the project settings for
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Select VHDL module and name the fil
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p1
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At the top click on Project → New
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Now that our code is finished we ha
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Programming the FPGA using iMPACT N
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If all is well, you should see the
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That's it! Your 2-bit greater-than
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Creating the Design First make sure
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Once Simulink is open make a new mo
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Now we will create a new compilatio
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Leave the board on and click 'Detec
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Click Save and Close, then click 'A
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Once the installation is complete,
Page 49 and 50: After dragging in the box, a window
Page 51 and 52: Double-click on the System Generato
Page 54 and 55: Click ok. Make sure your board is o
Page 56 and 57: Then you can toggle the GPIO switch
Page 58 and 59: Now within this folder make two emp
Page 60 and 61: In the Project File section point i
Page 62 and 63: Choose the development board, in ou
Page 64 and 65: Choose these default values for the
Page 66 and 67: Click Next on the Cache window as w
Page 68 and 69: The base system is now finished but
Page 70 and 71: Xilinx SDK Close Xilinx XPS and ope
Page 72 and 73: The Xilinx SDK will prompt you to s
Page 74 and 75: In the next window, name the projec
Page 76 and 77: Expand the 'src' folder under the '
Page 78 and 79: Now right-click on the hello_uart p
Page 80 and 81: Turn on the ML506 and open up a ser
Page 82 and 83: Create a folder on the local drive
Page 84 and 85: Then copy these files and put them
Page 86 and 87: Since this Xilinx project was creat
Page 88 and 89: Finally, click Finish: 88
Page 90 and 91: Xilinx SDK Close Xilinx XPS and ope
Page 92 and 93: Name the C project 'play_sine' and
Page 94 and 95: The files I will be using can be fo
Page 96 and 97: * local prototypes */ volatile int
Page 100 and 101: XIo_Out32(AC97_InFIFO, j); } } int
Page 102 and 103: Next we need to add some header fil
Page 104 and 105: Program the FPGA Turn on the ML506
Page 106 and 107: Some instructions are also displaye
Page 108 and 109: Create a folder on your local drive
Page 110 and 111: Now we need the bitstream of our pr
Page 112 and 113: Setting up the Compact Flash Make s
Page 114: Since our file is in cfg1, we need
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Tutorial Xilinx Virtex-5 FPGA ML506 Edition

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