Tutorial Xilinx Virtex-5 FPGA ML506 Edition

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* local prototypes */ volatile int data_in_buf_len; int data_in_buf[19]; volatile int dummy; volatile int cur_sound_len; volatile unsigned char *cur_sound_ptr; unsigned int sound_ptr; int c; int freq = 22; #define MY_AC97_BASEADDR XPAR_OPB_AC97_CONTROLLER_REF_0_BASEADDR #define AC97_InFIFO MY_AC97_BASEADDR #define AC97_OutFIFO MY_AC97_BASEADDR + 0x4 #define AC97_FIFO_Status MY_AC97_BASEADDR + 0x8 #define AC97_Control MY_AC97_BASEADDR + 0xC #define AC97_RegAddr MY_AC97_BASEADDR + 0x10 #define AC97_RegRead MY_AC97_BASEADDR + 0x14 #define AC97_RegWrite MY_AC97_BASEADDR + 0x18 #define AC97_InFIFO_Full 0x01 #define AC97_InFIFO_Half_Full 0x02 #define AC97_OutFIFO_Full 0x04 #define AC97_OutFIFO_Empty 0x08 #define AC97_Reg_Access_Finished 0x10 #define AC97_CODEC_RDY 0x20 #define AC97_REG_ACCESS 0x40 #define AC97_Enable_In_Intr 0x01 // AC97 CODEC Registers #define AC97_Reset 0x00 #define AC97_MasterVol 0x02 #define AC97_HeadphoneVol 0x04 #define AC97_MasterVolMono 0x06 #define AC97_Reserved0x08 0x08 #define AC97_PCBeepVol 0x0A #define AC97_PhoneInVol 0x0C #define AC97_MicVol 0x0E #define AC97_LineInVol 0x10 #define AC97_CDVol 0x12 #define AC97_VideoVol 0x14 #define AC97_AuxVol 0x16 #define AC97_PCMOutVol 0x18 #define AC97_RecordSelect 0x1A #define AC97_RecordGain 0x1C #define AC97_Reserved0x1E 0x1E #define AC97_GeneralPurpose 0x20 #define AC97_3DControl 0x22 #define AC97_PowerDown 0x26 #define AC97_ExtendedAudioID 0x28 #define AC97_ExtendedAudioStat 0x2A #define AC97_PCM_DAC_Rate0 0x78 #define AC97_PCM_DAC_Rate1 0x7A #define AC97_Reserved0x34 0x34 #define AC97_JackSense 0x72 #define AC97_SerialConfig 0x74 96
#define AC97_MiscControlBits #define AC97_VendorID1 #define AC97_VendorID2 0x76 0x7C 0x7E // Volume Constants #define AC97_VolMute 0x8000 #define AC97_VolMax 0x0000 #define AC97_VolMin 0x3F3F #define AC97_VolMid 0x1010 void WriteAC97Reg( int reg_addr, int value) { XIo_Out32 (AC97_RegWrite, value); XIo_Out32 (AC97_RegAddr, reg_addr); usleep (10000); } int ReadAC97Reg( int reg_addr) { XIo_Out32 (AC97_RegAddr, reg_addr | 0x80); usleep (10000); return XIo_In32(AC97_RegRead); } void init_sound() { printf("Initializing AC97 CODEC...\r\n"); // reset all reg's to known states (cause MUTE to all) WriteAC97Reg(AC97_Reset,0); usleep (1000); while (!(XIo_In32(AC97_FIFO_Status) & AC97_CODEC_RDY)) {}; xil_printf ("PowerDown Reg State (Should be 0x000F) = %x \n\r", ReadAC97Reg (AC97_PowerDown)); // turn on external amp xil_printf ("Turning on External Power Amp \n\r"); WriteAC97Reg(AC97_JackSense,0x3F00); // set Jack Sense Pins // powerdown DAC and ADC temporarily WriteAC97Reg(AC97_PowerDown,0x0300); usleep (1000000); // initialize LCD and write to it LCDOn(); LCDInit(); LCDPrintString ("1. 400Hz 2. 1kHz", "3. 5kHz"); xil_printf ("\n\r\n\rPick the frequency:\n\r"); xil_printf ("1. 400Hz\n\r2. 1kHz\n\r3. 5kHz\n\r\n\r\n\r"); while (!(XUartNs550_GetLineStatusReg(UART_BASEADDR) & 0x1)); do {freq = XUartNs550_RecvByte(UART_BASEADDR); } // check for invalid choices while (((char) freq != '1') && ((char) freq != '2') && ((char) freq != '3')); if ((char) freq == '1') freq = 110; if ((char) freq == '2') freq = 44; if ((char) freq == '3') freq = 9; 97
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Tutorial Xilinx Virtex-5 FPGA ML506
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Blank Page 3
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Setting up the ML506 board The ML50
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• Set SW6 (on the back side of th
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• Go to setup → serial port, an
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Illustration 1: SACE ERR, CF card i
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Once this is complete, right-click
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After connecting your board. Run Te
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The VHDL Design Open up Xilinx ISE.
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Now setup the project settings for
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Select VHDL module and name the fil
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p1
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At the top click on Project → New
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Now that our code is finished we ha
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Programming the FPGA using iMPACT N
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If all is well, you should see the
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That's it! Your 2-bit greater-than
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Creating the Design First make sure
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Once Simulink is open make a new mo
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Now we will create a new compilatio
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Leave the board on and click 'Detec
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Click Save and Close, then click 'A
Page 46: Once the installation is complete,
Page 49 and 50: After dragging in the box, a window
Page 51 and 52: Double-click on the System Generato
Page 54 and 55: Click ok. Make sure your board is o
Page 56 and 57: Then you can toggle the GPIO switch
Page 58 and 59: Now within this folder make two emp
Page 60 and 61: In the Project File section point i
Page 62 and 63: Choose the development board, in ou
Page 64 and 65: Choose these default values for the
Page 66 and 67: Click Next on the Cache window as w
Page 68 and 69: The base system is now finished but
Page 70 and 71: Xilinx SDK Close Xilinx XPS and ope
Page 72 and 73: The Xilinx SDK will prompt you to s
Page 74 and 75: In the next window, name the projec
Page 76 and 77: Expand the 'src' folder under the '
Page 78 and 79: Now right-click on the hello_uart p
Page 80 and 81: Turn on the ML506 and open up a ser
Page 82 and 83: Create a folder on the local drive
Page 84 and 85: Then copy these files and put them
Page 86 and 87: Since this Xilinx project was creat
Page 88 and 89: Finally, click Finish: 88
Page 90 and 91: Xilinx SDK Close Xilinx XPS and ope
Page 92 and 93: Name the C project 'play_sine' and
Page 94 and 95: The files I will be using can be fo
Page 98 and 99: WriteAC97Reg(AC97_ExtendedAudioStat
Page 100 and 101: XIo_Out32(AC97_InFIFO, j); } } int
Page 102 and 103: Next we need to add some header fil
Page 104 and 105: Program the FPGA Turn on the ML506
Page 106 and 107: Some instructions are also displaye
Page 108 and 109: Create a folder on your local drive
Page 110 and 111: Now we need the bitstream of our pr
Page 112 and 113: Setting up the Compact Flash Make s
Page 114: Since our file is in cfg1, we need
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