Tutorial Xilinx Virtex-5 FPGA ML506 Edition
Tutorial Xilinx Virtex-5 FPGA ML506 Edition
Tutorial Xilinx Virtex-5 FPGA ML506 Edition
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After selecting '<strong>ML506</strong>_twobitGreater' click Generate. This may take a while (5-10 mins).<br />
Once completed, System Generator will show a Co-Sim block, drag this block into your model<br />
editor.<br />
We can now simulate our design. In your model editor, click Simulation → Configuration<br />
Parameters.<br />
Set the stop time to: inf<br />
Set Solver to : discrete<br />
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