Tutorial Xilinx Virtex-5 FPGA ML506 Edition

In the define module screen change the architecture name to 'sop_arch' for sum-of-products
architecture. We have two inputs, a and b, each two bits wide and one output 'agreatb'. Click
Next and Finish.
Xilinx should now have created a VHDL template for use to write our code in. If you don't
see it double click on the file 'greater_2bit – sop_arch' in the hierarchy window.
Change the architecture definition to this:
architecture sop_arch of greater_2bit is
begin
signal p0, p1, p2 : std_logic;
agreatb