ncr/doc/RealPOS/7455/Technical_Manuals/7455_Re... - Alsys Data
ncr/doc/RealPOS/7455/Technical_Manuals/7455_Re... - Alsys Data
ncr/doc/RealPOS/7455/Technical_Manuals/7455_Re... - Alsys Data
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1-18 Chapter 1: Product Overview<br />
Because a hole in memory creates a non-contiguous address space,<br />
enabling linear addressing when total system DRAM is greater than<br />
64 MB is not recommended. Video linear addressing is enabled<br />
through PC Setup under the Integrated Peripherals menu.<br />
The processor also supports VESA standards such as the VESA DPMS<br />
protocol to place a DPMS compliant monitor into power savings<br />
modes.<br />
<strong>Re</strong>solutions Supported<br />
<strong>Re</strong>solution Colors Max Vfreq<br />
800x600x8bpp 256 85 Hz<br />
800x600x16bpp 64 K 85 Hz<br />
800x600x24bpp 16 M 85 Hz<br />
Colors Supported<br />
<strong>Re</strong>solution<br />
256 Colors<br />
(8-Bit)<br />
65,000 Colors<br />
(16-Bit)<br />
16.7 M Colors<br />
(24-Bit)<br />
800x600 512 K 1 MB 2 MB<br />
Board BIOS<br />
The Processor Board uses a Phoenix BIOS, which is stored in Flash<br />
ROM and easily upgraded through the network connection or serial<br />
port. The Flash EEPROM also contains the Setup utility, Power-On Self<br />
Tests (POST), and APM 1.2. The board also supports system BIOS<br />
shadowing, allowing the BIOS to execute from on-board writeprotected<br />
DRAM.<br />
The BIOS displays a sign-on message during POST, identifying the<br />
type of BIOS and a five-digit revision code.
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