Synopsys PowerPC for developerWorks - IBM

Synthesizable “Power” – 

Using Process Portability to Embed 

PowerPC Cores in Your Chip 

Lonn Fiance 

Director, Strategic Alliances 

Synopsys

Agenda 

• Synopsys overview 

• PowerPC embedded core overview 

• Synopsys’ Synthesizable PowerPC 

405/440 offering 

• Questions and answers 

© 2005 Synopsys, Inc. Pg. 2;

Global leader in EDA and IP 

1400 

1200 

$1.1B revenue in FY04 

1000 

800 

600 

400 

200 

0 

FY96 FY97 FY98 FY99 FY00 FY01 FY02 FY03 FY04 

• Strong global presence: 

• ~ 4,400 employees, 60+ offices 

• Strong technical innovation: 

• 1600+ R&D eng. (~26% of rev.) 

• Strong customer support: 

• 1450+ applications engineers 

350 

300 

250 

200 

150 

100 

50 

0 

$285M on R&D in FY04 

FY96 FY97 FY98 FY99 FY00 FY01 FY02 FY03 FY04 


Synopsys in China Since 

1995 

P 

Synopsys Offices 

National IC Design 

Incubation Centers 

University Programs 

35 locations 

200+ R&D Engineers 

Partnerships 

Chengdu 

University of Electronics Science 

and Technology of China 

Xian Jiaotong 

University 

Xi’an 

P 

Datang 

Telecom 

Wuxi 

Hangzhou 

Zhejiang University 

Chinese 

Academy 

of Sciences 

P 

SMIC 

Harrbin University 

Beijing 

Tsinghua University 

Beijing Polytechnical University 

Northern JiaoTong University 

Peking University 

Beijing College of Aeronautics 

P 

Shanghai 

Shanghai Jiao Tong University 

Tongji University 

Fudan University 

Shenzhen 

HKUST, HKUC, SCUST 

Hong Kong 


Most Trusted in EDA Industry 

Attribute in selecting vendor 

Best after-sales support 

Offers competitive prices 

Technology leader today 

Technology leader in 3 years 

Best support of open standards 

Best integration w/other tools 

Best integration with foundries & IP suppliers 

Clear vision of future 

Most ethical company 

Best documentation 

Knowledgeable sales reps 

Well-managed company 

Best training services 

Best before-sales system support 

Best Web site 

Offers consulting design services 

SNPS Rank 

1 

3 

1 

1 

2 

2 

1 

1 

1 

1 

1 

1 

1 

2 

1 

2 

7% 

7% 

12% 

Importance 

24% 

23% 

23% 

28% 

37% 

36% 

35% 

33% 

32% 

46% 

39% 

61% 

59% 

© 2005 Synopsys, Inc. Pg. 5; 

Source: 2004 EE Times Reader EDA Survey

Need Convergent Optimization Solution 

QOR 

TTR 

Area 

Signal Integrity 

Signal Integrity 

Power 

Test 

Yield 

COR 


Complete, Correlated And Concurrent 

IP Reuse 

Design 

Verification 

Flows 

DFM 

& Services 


Industry Leading Alliances 

Foundries 

ASIC Vendors 

PLD Vendors 

IP Vendors 

Library Vendors 

Synopsys strategic 

partnerships assure our 

customers meet their 

performance, cost, and 

schedule goals. 


Power Architecture Application Areas 

970 

970 

970 

750 

WAN 

Switch/Router 

750 

Server 

970 

750 

440 

Workstations 

750 

440 

440 Games 

440 

3G Access / IP 

Gateway 

GPS, In-cabin, 

& Telematics 

PDA 

Set-Top Box 

Wireless LAN 

405 

Networking 

Networked 

Storage 

IT/Storage 

440 

405 

Personal 

Communicator 405 

Digital 

405 

Imaging 

In Auto In Hand In Home 

Pervasive Computing 


IBM PowerPC ® Licensable Cores 

Key Features 

•32-bit PowerPC Book E 

•Superscalar, 2 inst/cycle 

•MMU, 1KB-256MB pages 

•128-bit PLB, 64GB addr 

PowerPC 440 

1.5mW/MHz 

2.5mW/MHz 

440 440 

32K/32K 

0.18um 

15.5mm 2 

32K/32K 

130nm 

9.8mm 2 

440-S 

32K/32K 

Fully 

Synthesizable 

PowerPC 405 

1.9mW/MHz 

16K/16K 

0.18um 

8.0mm 2 

0.9mW/MHz 

405 405 405-S 

16K/16K 

130nm 

3.8mm 2 

16K/16K 

Fully 

Synthesizable 

Key Features 

•32-bit PowerPC Embedded 

•Scalar, 1 inst/cycle 

•MMU, 1KB-16MB pages 

•64-bit PLB, 4GB addr 


PowerPC 405 Features 

Architecture 

Special 

Features 

CPU 

Pipeline 

Caches 

MMU 

Branch 

Pred. 

Physical 

Address 

Debug 


32-bit PowerPC Embedded 

Application code compatible with all PowerPC 

microprocessors 

Hardware multiply / divide 

24 DSP instructions (16x16+32) 

32-bit x 32 general purpose registers 

5 Stage Pipeline 

Single instruction per cycle 

16KB, 2-way set associative, 32-byte line, no 

locking, parity 

64 entry UTLB – full associativity 

4 entry ITLB, 8 entry DTLB 

5 cycle miss penalty 

Variable pages – 1KB to 16MB 

Static 

32-bit (4GB physical address) 

64- or 128-bit interface to Processor Local Bus 

(PLB) 

On-chip memory supported via PLB 

JTAG and Trace FIFO ports 

Real-time, non-invasive trace supported 

64b Processor Local Bus 


16K 

16K 

I-cache 

I-cache 

I-cache 

I-cache 

control 

control 

Instruction 

Instruction 

Unit 

Unit 

Execution 

Execution 

Unit 

Unit 

MAC 

MAC 

MMU 

MMU 

Branch 

Branch 

Unit 

Unit 

GPRs 

GPRs 

16K 

16K 

D-cache 

D-cache 

D-cache 

D-cache 

control 

control 

Timers Power Management 


Debug / Trace Interrupts 

Debug / Trace Interrupts

PowerPC 440 Features 

Architecture 

CPU Pipeline 

L1 Caches 

MMU 

Branch Pred. 

Physical Addr 

Core Interfaces 

Debug 

32-bit PowerPC Book E 

Application code compatible with all 

PowerPC microprocessors 

Two-way superscalar 

7 Stages, out of order issue, execution and 

completion 

32KB, 64-way set associative, transient and 

locked cache region mechanism, software 

managed coherency, parity 

64 entry UTLB – full associativity 

4 entry ITLB, 8 entry DTLB 

3 cycle ITLB/DTLB miss penalty 

Dynamic 

16-entry BTAC, 4K-entry BHT 

36-bit (64GB physical address) 

Three independent 128-bit PLB4 master 

ports (instruction read, data read, data 

write), each with separate address bus 

JTAG and Trace FIFO ports 

Real-time, non-invasive trace supported 



32K 

32K 

I-cache 

I-cache 

I-cache 

I-cache 

control 

control 

Instruction Unit 

Instruction Unit 

Complex 

Complex 

Integer 

Integer 

Pipe 

Pipe 

MAC 

MAC 

MMU 

MMU 

Simple 

Simple 

Integer 

Integer 

Pipe 

Pipe 

32K 

32K 

D-cache 

D-cache 

Branch 

Branch 

Unit 

Unit 

D-cache 

D-cache 

control 

control 

Load / 

Load / 

Store 

Store 

Pipe 

Pipe 






The Power of Flexibility 

• Each application has unique requirements 

• Business: cost, delivery time, existing 

supplier relationships, design services, etc. 

• Technical: process technology, integration, 

packaging, performance, other IP, etc. 

• Life cycle: process migration, multisourcing, 

cost reductions, strategic options 

• Process portability provides flexibility to 

address these requirements 

• Flexibility is key to proliferation 


Flexibility Creates Value 

• Design Value is a 

complicated function 

Value = f(Area, 

Performance, Power, 

Yield, IP, Packaging, 

Process, Delivery Time, 

Reliability, Risk, 

Location) 

• Complex interaction 

between the parameters 

• Intelligent tradeoffs 

increase value 

• Design specific 

Performance 

Example Trade-Offs 

Area or 

Power 


PowerPC 405-S & 440-S Overview 

• Macro Objective: 

• Technology independent, reusable 

and fully synthesizable PowerPC 

cores 

• Design Objectives 

• Standard SRAM’s and Register Files 

for Caches and UTLB’s 

• Maintain cycle compatibility with the existing PowerPC 4xx 

• Target performance of 300 MHz (440-S) and 250 MHz (405-S) for 

Artisan TSMC 13 LVFSG 

• Fault coverage goal of >98% 

• Use a complete Synopsys tool flow 

• Verification Objectives 

• Create a portable verification environment 

2.5mW/MHz 

• Create tests to verify the major architectural capabilities 

• Easy delivery and use via Synopsys DesignWare ® 

440 

32K/32K 

180nm 

15.5mm 2 

1.9mW/MHz 

405 

16K/16K 

180nm 

8.0mm 2 

1.5mW/MHz 

440 440-S 

32K/32K 

130nm 

9.8mm 2 

0.9mW/MHz 

405 405-S 

16K/16K 

130nm 

3.8mm 2 

32K/32K 

Fully 

Synthesizable 

16K/16K 

Fully 

Synthesizable 


Synopsys Power Solution - 

Design Flexibility and Portability 

• System C models 

• System-level SystemC models 

• Instrumented for System Studio 

• SoC Design 

• Design View 

• Implementation View 

• CPU, SoC testbenches with test suites 

• Documentation 

• Implementation scripts with README’s 

• User Guide, Data Book, App Notes, etc. 

• Support 

• Award-winning customer support 

• Qualified design services and complimentary IP 


SystemC Models 

• C++ class library to model SoC hardware 

and processes 

• Used for system-level design 

• Architectural analysis of processors, buses, 

custom logic, and IP 

• Explore hardware/software tradeoffs 

• SystemC is an open industry standard 

• Tool and IP support from multiple companies 

• C++ basis allows concurrent development 

of hardware and software 


Synopsys SystemC Deliverables 

• Original models, 

testing and 

validation from IBM 

• Synopsys 

distributes and 

supports 

• Instrumented for 

System Studio 

SystemC Model List 

• PowerPC 405 Processor Core 

• PowerPC 440 Processor Core 

• PLB4 (Processor Local Bus v4.x) 

• DMA Controller (PLB4) 

• DCR (Device Control Register) 

• UIC (Universal Interrupt Controller) 

• UART (Universal Asynchronous 

Receiver Transmitter) 

• MCMAL PLB4 (Multi-channel 

Memory Access Layer) 

• Memory (DDR) Controller (PLB4) 

• EBC (External Bus Controller) 

• OPB (On Chip Peripheral Bus) 

• PLB4 to OPB Bridge 

• OPB to PLB4 Bridge 

• PCI-X to PLB4 

• PCI-Express 


ICU Rd DCU Rd DCU Wr 

Design View coreKit Overview 

• “Black Box” Verilog Models for the 

PowerPC 4xx-S 

• Fixed configuration to determine 

feasibility 

• Cycle compatible VMC model of the 4xx-S 

• VERA based CPU testbench 

• Timing model for WC operating conditions 

for Artisan TSMC 13 LVFSG 

• All appropriate documentation (databook, 

datasheet, etc.) 

• PLB-to-AHB Bridge Verilog Model 

• Cycle compatible VMC model of the 

PLB2AHB Bridge 

• VERA based SOC testbench for the 


• Application note 

• Available to DesignWare licensees 

at no additional charge 


PLB 

DW AMBA VIP 

AHB 

Arbiter 

Arbiter 

PLB 

Monitor 

AHB 

Master1 

DW AMBA VIP 

PLB 

M aster 

AHB 

Monitor 

Verilog Toplevel 

Testbench 

VERA Models 

hclk 

SYS_plbClk 

dcr_clk 

Backend Interface 

PLB 

Monitor 

Interrupt 

Ctrl Model 

JTAG 

Model 

DCR 

Model 

AHB 

Master3 

PLB 

Slave1 

Inte rru p t pin s 

JT A G Interface 

DCR Bus 

DCR 

Monitor 

PLB (128-bits) 


(PLB Slave 3) 

(AHB M aster 2) 

PLB Slave/ 

Backend 

Control 

Processor Processor Local Local Bus Bus (PLB) 

PLB 

Slave2 

AHB (32/64/128-bits) 

AHB 

Slave1 

440 Core 

Clock and 

Reset Logic 

PLB M aster 

(PPC440) 

DCR 

AHB 

Slave2 

These IP's are not delivered as a part of the corekit, but has to be installed 

separately. However the testbench will be instantiating these com ponents. 

IB M P L B 

Slave Model 

(m em ory) 

IBM PLB Model Toolkit 

DCR 

Monitor 

DCR 

Slave 

DCR 

Slave 

AHB 

Slave3 

DCR 

DCR 

IB M 

PLB 

Arbiter

Testbench - 440-S CPU 

Verilog Toplevel 

Testbench 

Backend Interface 

PLB Slave/ 

Backend 

Control 

IB M P L B 

Slave Model 

(m em o ry) 

PLB 

Monitor 

Processor Processor Local Local Bus Bus (PLB) 

IB M 

PLB 

Arbiter 

Interrupt 

Ctrl Model 

In te rru p t p in s 

ICU Rd DCU Rd DCU Wr 

JTAG 

Model 

JT A G In terface 

440 Core 

DCR 

Model 

DCR Bus 

VERA Models 

DCR 

Monitor 

Clock and 

Reset Logic 


Testbench - PLB/AHB SOC 

IBM PLB Model Toolkit 

PLB 

Monitor 

PLB 

Master 

PLB 

Slave1 

PLB 

Slave2 

PLB M aster 

(PPC440) 

PLB 

Arbiter 

PLB (128-bits) 

DCR 

Monitor 

DCR 

DCR 

hclk 

SYS_plbClk 

dcr_clk 


(PLB Slave 3) 

(AHB M aster 2) 

DCR 

DCR 

Slave 

DCR 

Slave 

DW AMBA VIP 

AHB 

Arbiter 

AHB (32/64/128-bits) 

AHB 

Master1 

AHB 

Master3 

AHB 

Slave1 

AHB 

Slave3 

DW AMBA VIP 

AHB 

Monitor 

AHB 

Slave2 

These IP's are not delivered as a part of the corekit, but has to be installed 

separately. However the testbench will be instantiating these com ponents. 


Implementation View coreKit Overview 

• RTL source for PowerPC core and PLB-to-AHB Bridge 

• Configurable via coreAssembler 

• Portable RTL validated by both IBM and Synopsys 

• Implementation scripts with documentation 

• RTL simulation in an automated verification environment 

• Default floor plans 

• Integration of technology specific RAMs 

• Logical and physical synthesis with clock tree synthesis 

• Scan insertion and ATPG 

• Formal verification 

• Power optimization and analysis 

‣ Complete RTL-to-GDSII capability 

• Documentation for SoC integration 

• User Guide, Data Book 

• App Notes 

• Licensing 

• PowerPC license from IBM 

• DesignWare license from Synopsys 

128-bit Processor Local Bus 

32KB 

I-cache 

w/parity 

I-cache 

Control 

Instruction 

Unit 

Complex 

Integer 

Pipe 

MAC 

Timers 

Debug/Trace 

MMU 

Simple 

Integer 

Pipe 

32KB 

D-cache 

w/parity 

Branch 

Unit 

D-cache 

Control 

Load / 

Store 

Pipe 

Power Management 

Interrupts 

PowerPC 440 Core 


Design View Flow 

Install Design 

View coreKit 

Create coreConsultant 

workspace 

Implementation View Flow 

Install Implementation 

View coreKit 

Create coreConsultant 

workspace 

Configure RTL 

Install VMC Model 

Simulate VMC Model 

in standalone verification environment 

Simulate VMC Model 

in application verification environment 

Synthesize application logic using 

PowerPC 4xx Star IP CPU’s timing 

model to check approximate timing 

Get Implementation 

View coreKit 

Simulate configured RTL in 

standalone verification 

environment 

Simulate configured RTL in 

application verification 

environment 

Run STA 

Formally verify gatelevel 

netlist 

Simulate gate-level netlist 

Perform power analysis 

Integrate technology 

specific RAMs 

Synthesize (RTL-togates) 

Insert scan 

Create floorplan 

Run physical synthesis 

Create test vectors 


Synopsys Tool Support in coreKit 

Product 

VCS ® 

Vera 

Design Compiler ® 

Physical Compiler ® 

JupiterXT 

Astro 

DFT Compiler 

TetraMAX ® 

DesignWare BIST 

Power Compiler 

PrimePower 

Capability 

RTL simulation 

Verification Testbench 

Logic synthesis 

Physical synthesis 

Design planning 

CTS scripts for detailed placement and 

routing 

Design-for-test insertion 

Test pattern generation 

Built-In-Self-Test capability 

Power optimization 

Full-chip power analysis 


Default IBM PowerPC 440-S 

Floorplan 


32KB 

I-cache 

w/parity 

32KB 

D-cache 

w/parity 

DCA 

top array 

DCA 

bottom array 

I-cache 

Control 

MMU 

D-cache 

Control 

UTLB 

Instruction 

Unit 

Branch 

Unit 

ICA 

top array 

BHT SRAM 

ICA 

bottom array 

Complex 

Integer 

Pipe 

MAC 

Timers 

Debug/Trace 

Simple 

Integer 

Pipe 

Load / 

Store 

Pipe 

Power Management 

Interrupts 

PowerPC 440 Core 


Default IBM PowerPC 405-S 

Floorplan 


I Cache 

I Cache 

16K 

I-cache 

16K 

D-cache 

I-cache 

control 

MMU 

D-cache 

control 

Instruction 

Unit 

Branch 

Unit 

D Cache 

D Cache 

Execution 

Unit 

GPRs 

MAC 

Timers 

Power Mgmt 

Debug/Trace 

Interrupts 


Synopsys DesignWare ® IP portfolio 

DesignWare Star IP 

DesignWare 

IBM PowerPC 440 

On-Chip Bus 

Datapath, AMBA IP, Memory, 

Verification IP, Building 

Block IP, 8051, 6811, etc. 

DesignWare Library 

DesignWare Cores 

PCI Express, PCI-X, 

USB 2.0, USB OTG, 

IEEE 1394, etc. 

DesignWare 

Verification 

Library 

AMBA 

PCI Express 

PCI 

PCI-X 

Serial I/O 

USB 2.0 

IEEE 1394 

Ethernet 

Memory 

etc. 




DesignWare Verification Library 

Microprocessor cores from leading Star IP providers 

Infrastructure IP, including high-speed datapath generators 

Portfolio of digital and analog connectivity IP 

Simulation models of buses & I/O standards 


Benefits for PowerPC in DesignWare 

• Broad Availability 

• 25,000+ DesignWare users 

worldwide 

• Availability of supporting 

IP components 


DesignWare 

IBM PowerPC440/405 

• Fully Integrated with AMBA peripherals 

• AMBA AHB/APB w/ automated subsystem assembly 

• All DesignWare peripherals supported 

On-Chip Bus 

Datapath, AMBA IP, Memory, 

Verification IP, Building 

Block IP, 8051, 6811, etc. 


• Native CoreConnect interface retained and supported 

• Industry recognized first-tier customer support 

• Experienced technical support infrastructure 

• Tested with complete design flow 


PCI Express, PCI -X, 

USB 2.0, USB OTG, 

IEEE 1394, etc. 

DesignWare 

Verification 

Library 

AMBA 

PCI Express 

PCI 

PCI-X 

Serial I/O 

USB 2.0 

IEEE 1394 

Ethernet 

Memory 

etc. 


Summary 

• All program objectives achieved 

• Cycle compatibility with existing 440 and 405 cores 

• Single cycle cache access 

• Target performance of 300 MHz (440-S) and 250 MHz 

(405-S) achieved 

• Portable verification environment and critical test 

cases packaged in core delivery 

• Synopsys is a “one-stop shop” for synthesizable 

PowerPC 440 and 405 cores 

• Complete tool flow from RTL to CTS 

• Knowledge of CoreConnect and AMBA peripherals 

• Supported through DesignWare 

• Synopsys Professional Services are experts in 

PowerPC core and system implementations 


Synopsys and Power 

A Complete and Flexible Solution 

Complete Synopsys Solution 

Partners 

IBM 

Power.org 

Foundries 

Services 

PowerPC experience 

Low power, SoC design 

Complete Flow Expertise 

Tools 

IP 

Distribution & support (DesignWare) 

Proven Reusability Methodology 

#1 Connectivity IP provider 

Core Connect and AMBA IP 

System-Level Design Capability 

Complete Functional Verification 

Complete PowerPC and SoC Implementation Flow 

Post GDS Solution (OPC, PSM, fracturing)

Synopsys PowerPC for developerWorks - IBM

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