Low-Power Logic Synthesis
Low-Power Logic Synthesis
Low-Power Logic Synthesis
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Circuit Level Techniques<br />
• Transistor sizing<br />
– Trade silicon area for speed and/or power<br />
• Special flip-flop and latch<br />
– Reduce power in storage elements<br />
• Special logic family<br />
– PPRPL<br />
– PCFL3<br />
– DyCML<br />
– SCSL<br />
– Etc.<br />
NCHUCS 9
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