Low-Power Logic Synthesis
Low-Power Logic Synthesis
Low-Power Logic Synthesis
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<strong>Low</strong>-<strong>Power</strong> Design Techniques<br />
• Can be applied in any<br />
level of the design process<br />
• Various technologies can<br />
be applied simultaneously<br />
• Goal of optimization<br />
– Reduce C L<br />
– Reduce V DD<br />
– Reduce N<br />
– Clock frequency is NOT a<br />
target<br />
Architectural<br />
RTL<br />
<strong>Logic</strong><br />
Circuit<br />
Physical<br />
NCHUCS 5
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